diff options
| author | Jakub Jelinek <jakub@redhat.com> | 2022-02-12 11:17:41 +0100 |
|---|---|---|
| committer | Jakub Jelinek <jakub@redhat.com> | 2022-02-12 11:17:41 +0100 |
| commit | 0538d42cdd68f6b65d72ed7768f1d00ba44f8631 (patch) | |
| tree | 41b472d762e23f8e06d22612b0a49728fc293e7a | |
| parent | edadc7e0510b703d9727cf5ff68d55d84bb95def (diff) | |
| download | gcc-0538d42cdd68f6b65d72ed7768f1d00ba44f8631.zip gcc-0538d42cdd68f6b65d72ed7768f1d00ba44f8631.tar.gz gcc-0538d42cdd68f6b65d72ed7768f1d00ba44f8631.tar.bz2 | |
i386: Fix up cvtsd2ss splitter [PR104502]
The following testcase ICEs, because AVX512F is enabled, AVX512VL is not,
and the cvtsd2ss insn has %xmm0-15 as output operand and %xmm16-31 as
input operand. For output operand %xmm16+ the splitter just gives up
in such case, but for such input it just emits vmovddup which requires
AVX512VL if either operand is EXT_REX_SSE_REG_P (when it is 128-bit).
The following patch fixes it by treating that case like the pre-SSE3
output != input case - move the input to output and do everything on
the output reg which is known to be < %xmm16.
2022-02-12 Jakub Jelinek <jakub@redhat.com>
PR target/104502
* config/i386/i386.md (cvtsd2ss splitter): If operands[1] is xmm16+
and AVX512VL isn't available, move operands[1] to operands[0] first.
* gcc.target/i386/pr104502.c: New test.
| -rw-r--r-- | gcc/config/i386/i386.md | 4 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/i386/pr104502.c | 31 |
2 files changed, 33 insertions, 2 deletions
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 74da0d4..8ffa641 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -4838,8 +4838,8 @@ movddup is available. */ if (REG_P (operands[1])) { - if (!TARGET_SSE3 - && REGNO (operands[0]) != REGNO (operands[1])) + if ((!TARGET_SSE3 && REGNO (operands[0]) != REGNO (operands[1])) + || (EXT_REX_SSE_REG_P (operands[1]) && !TARGET_AVX512VL)) { rtx tmp = lowpart_subreg (DFmode, operands[0], SFmode); emit_move_insn (tmp, operands[1]); diff --git a/gcc/testsuite/gcc.target/i386/pr104502.c b/gcc/testsuite/gcc.target/i386/pr104502.c new file mode 100644 index 0000000..7a6eb26 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr104502.c @@ -0,0 +1,31 @@ +/* PR target/104502 */ +/* { dg-do compile { target fstack_protector } } */ +/* { dg-options "-O -flive-range-shrinkage -march=barcelona -fstack-protector-all -mavx512f" } */ + +typedef char __attribute__((__vector_size__ (8))) U; +typedef int __attribute__((__vector_size__ (8))) A; +typedef int __attribute__((__vector_size__ (16))) B; +typedef int __attribute__((__vector_size__ (32))) C; +typedef int __attribute__((__vector_size__ (64))) D; +typedef __float128 __attribute__((__vector_size__ (32))) F; + +char s; +U u; +A a; +int i; +C c; +double d; + +U +foo (U u0, A a0, B b0, B b1, C c0, C c1, C c2, C c3, A a1, A a2, F f0) +{ + C ca = c |= (short) (float) d; + C cb = c0 + c1 + c2 + c3 + ca + (C) f0; + U ua = s << (u & 4); + B ba = ((union {C a; B b;}) cb).b + b0 + b1; + U ub = ((union {B a; U b;}) ba).b + + u0 + u + ua + (U) a + (U) a + (U) a0 + (U) a1 + (U) a2; + long long u64_r = i + d; + char u8_r = u64_r; + return ub + u8_r; +} |