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| author | Jeff Law <jlaw@ventanamicro> | 2023-03-21 09:18:44 -0600 |
|---|---|---|
| committer | Jeff Law <jlaw@ventanamicro> | 2023-03-21 09:18:44 -0600 |
| commit | ea6aa4d94659e28881465532ca3b0d5a67bb166f (patch) | |
| tree | ed27f1648668b2917c0524871675d1540222d151 | |
| parent | acd5ecb0d9a7a8d130e85cffda4963b21c3e2442 (diff) | |
| download | gcc-ea6aa4d94659e28881465532ca3b0d5a67bb166f.zip gcc-ea6aa4d94659e28881465532ca3b0d5a67bb166f.tar.gz gcc-ea6aa4d94659e28881465532ca3b0d5a67bb166f.tar.bz2 | |
NFC: Formatting fixes
| -rw-r--r-- | gcc/config/riscv/bitmanip.md | 66 |
1 files changed, 35 insertions, 31 deletions
diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md index 2a9202d..974bf0b 100644 --- a/gcc/config/riscv/bitmanip.md +++ b/gcc/config/riscv/bitmanip.md @@ -658,8 +658,8 @@ (define_insn "clmul<mode>3" [(set (match_operand:X 0 "register_operand" "=r") -(clmul:X (match_operand:X 1 "register_operand" "r") -(match_operand:X 2 "register_operand" "r")))] + (clmul:X (match_operand:X 1 "register_operand" "r") + (match_operand:X 2 "register_operand" "r")))] "TARGET_ZBC" "clmul\t%0,%1,%2" [(set_attr "type" "bitmanip")]) @@ -667,8 +667,8 @@ (define_insn "clmulh<mode>3" [(set (match_operand:X 0 "register_operand" "=r") -(plus:X (match_operand:X 1 "register_operand" " r") -(match_operand:X 2 "register_operand" "r")))] + (plus:X (match_operand:X 1 "register_operand" " r") + (match_operand:X 2 "register_operand" "r")))] "TARGET_ZBC" "clmulh\t%0,%1,%2" [(set_attr "type" "bitmanip")]) @@ -676,38 +676,42 @@ (define_insn "clmulr<mode>3" [(set (match_operand:X 0 "register_operand" "=r") -(clmulr:X (match_operand:X 1 "register_operand" "r") -(match_operand:X 2 "register_operand" "r")))] + (clmulr:X (match_operand:X 1 "register_operand" "r") + (match_operand:X 2 "register_operand" "r")))] "TARGET_ZBC" "clmulr\t%0,%1,%2" [(set_attr "type" "bitmanip")]) (define_expand "crcqihi4" [(match_operand:HI 1) -(match_operand:QI 2) -(match_operand:HI 3)] + (match_operand:QI 2) + (match_operand:HI 3)] "" { -if (TARGET_ZBC) - { - // Instruction sequence from slides. Sizes need to be fixed. - rtx a0 = operands[1], a1 = operands[2]; - unsigned HOST_WIDE_INT - q = gf2n_poly_long_div_quotient (UINTVAL (operands[3])); - rtx t0 = gen_rtx_CONST (SImode, GEN_INT (q)); - rtx t1 = gen_rtx_CONST (SImode, operands[3]); - a0 = force_reg (SImode, gen_rtx_XOR (SImode, a0, a1)); - a0 = force_reg (SImode, gen_rtx_CLMUL (SImode, a0, t0)); - a0= force_reg (SImode, gen_rtx_ASHIFT (SImode, a0, GEN_INT (16))); - a0 = force_reg (SImode, gen_rtx_CLMUL (SImode, a0, t1)); - a0 = force_reg (SImode, gen_rtx_LSHIFTRT (SImode, a0, GEN_INT (24))); - a0= force_reg (SImode, gen_rtx_ASHIFT (SImode, a0, GEN_INT (24))); - rtx tgt = simplify_gen_subreg (SImode, operands[0], HImode, 0); - emit_move_insn (tgt, a0); - } -else - { - expand_crc_table_based (operands, QImode); - } -DONE; -})
\ No newline at end of file + if (TARGET_ZBC) + { + // Instruction sequence from slides. Sizes need to be fixed. + rtx a0 = operands[1]; + rtx a1 = operands[2]; + unsigned HOST_WIDE_INT q + = gf2n_poly_long_div_quotient (UINTVAL (operands[3])); + rtx t0 = gen_rtx_CONST (SImode, GEN_INT (q)); + rtx t1 = gen_rtx_CONST (SImode, operands[3]); + a0 = force_reg (SImode, gen_rtx_XOR (SImode, a0, a1)); + a0 = force_reg (SImode, gen_rtx_CLMUL (SImode, a0, t0)); + a0 = force_reg (SImode, gen_rtx_ASHIFT (SImode, a0, GEN_INT (16))); + a0 = force_reg (SImode, gen_rtx_CLMUL (SImode, a0, t1)); + a0 = force_reg (SImode, gen_rtx_LSHIFTRT (SImode, a0, GEN_INT (24))); + a0 = force_reg (SImode, gen_rtx_ASHIFT (SImode, a0, GEN_INT (24))); + rtx tgt = simplify_gen_subreg (SImode, operands[0], HImode, 0); + emit_move_insn (tgt, a0); + } + else + { + /* If we do not have the ZBC extension (ie, no clmul), then + use a table based algorithm to implement the CRC. */ + expand_crc_table_based (operands, QImode); + } + + DONE; +}) |