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| author | Andrew Pinski <apinski@marvell.com> | 2022-08-15 18:39:17 +0000 |
|---|---|---|
| committer | Andrew Pinski <apinski@marvell.com> | 2022-08-24 12:15:32 -0700 |
| commit | 95989ab39bbedd34e6f508de3109cb5c17db433e (patch) | |
| tree | 8fd16f0ab40f9451beb402f33aab7b8a777f9acd | |
| parent | b7d4b734f2d81eccb67903e4fa8f94249238d39c (diff) | |
| download | gcc-95989ab39bbedd34e6f508de3109cb5c17db433e.zip gcc-95989ab39bbedd34e6f508de3109cb5c17db433e.tar.gz gcc-95989ab39bbedd34e6f508de3109cb5c17db433e.tar.bz2 | |
[RISCV] Use a constraint for bset<mode>_mask and bset<mode>_1_mask
A constraint here just makes it easier to understand what the
operands are.
OK? Built and tested on riscv32-linux-gnu and riscv64-linux-gnu with
--with-arch=rvNimafdc_zba_zbb_zbc_zbs (where N is 32 and 64).
Thanks,
Andrew Pinski
gcc/ChangeLog:
* config/riscv/constraints.md (DsS): New constraint.
(DsD): New constraint.
* config/riscv/iterators.md (shiftm1c): New iterator.
* config/riscv/bitmanip.md (*bset<mode>_mask):
Use shiftm1c.
(*bset<mode>_1_mask): Likewise.
| -rw-r--r-- | gcc/config/riscv/bitmanip.md | 4 | ||||
| -rw-r--r-- | gcc/config/riscv/constraints.md | 12 | ||||
| -rw-r--r-- | gcc/config/riscv/iterators.md | 1 |
3 files changed, 15 insertions, 2 deletions
diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md index 258bd5a..73b2c10 100644 --- a/gcc/config/riscv/bitmanip.md +++ b/gcc/config/riscv/bitmanip.md @@ -297,7 +297,7 @@ (ior:X (ashift:X (const_int 1) (subreg:QI (and:X (match_operand:X 2 "register_operand" "r") - (match_operand 3 "<X:shiftm1>" "i")) 0)) + (match_operand 3 "<X:shiftm1>" "<X:shiftm1p>")) 0)) (match_operand:X 1 "register_operand" "r")))] "TARGET_ZBS" "bset\t%0,%1,%2" @@ -316,7 +316,7 @@ (ashift:X (const_int 1) (subreg:QI (and:X (match_operand:X 1 "register_operand" "r") - (match_operand 2 "<X:shiftm1>" "i")) 0)))] + (match_operand 2 "<X:shiftm1>" "<X:shiftm1p>")) 0)))] "TARGET_ZBS" "bset\t%0,x0,%1" [(set_attr "type" "bitmanip")]) diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md index 61b84875..444870a 100644 --- a/gcc/config/riscv/constraints.md +++ b/gcc/config/riscv/constraints.md @@ -60,6 +60,18 @@ (and (match_code "const_int") (match_test "IN_RANGE (ival, 1, 3)"))) +(define_constraint "DsS" + "@internal + 31 immediate" + (and (match_code "const_int") + (match_test "ival == 31"))) + +(define_constraint "DsD" + "@internal + 63 immediate" + (and (match_code "const_int") + (match_test "ival == 63"))) + ;; Floating-point constant +0.0, used for FCVT-based moves when FMV is ;; not available in RV32. (define_constraint "G" diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md index 2d7223d..39dffab 100644 --- a/gcc/config/riscv/iterators.md +++ b/gcc/config/riscv/iterators.md @@ -114,6 +114,7 @@ ; bitmanip mode attribute (define_mode_attr shiftm1 [(SI "const31_operand") (DI "const63_operand")]) +(define_mode_attr shiftm1p [(SI "DsS") (DI "DsD")]) ;; ------------------------------------------------------------------- ;; Code Iterators |