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authorChenghua Xu <paul.hua.gm@gmail.com>2018-11-07 10:29:52 +0000
committerChenghua Xu <paulhua@gcc.gnu.org>2018-11-07 10:29:52 +0000
commitf70b5dbfa111f03dd31a3e3bd2e3d01eecdc06c3 (patch)
tree71e071c212eb4cc74475e0c99366ed9ea8f8b47f
parent36b56cd336f50d1565ecc4c5b1fed89151392baf (diff)
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Fix some typo and brain twister logical.
gcc/ * config/mips/mips.c: Fix typo in documentation of mips_loongson_ext2_prefetch_cookie. (mips_option_override): fix brain twister logical. * config/mips/mips.h: Fix typo in documentation of ISA_HAS_CTZ_CTO and define pattern. * config/mips/mips.md (prefetch): Hoist EXT2 above the 2EF/EXT block. (prefetch_indexed): Hoist EXT2 above the EXT block. gcc/testsuite/ * gcc.target/mips/loongson-ctz.c: Fix typo. * gcc.target/mips/loongson-dctz.c: Fix typo. From-SVN: r265871
-rw-r--r--gcc/ChangeLog11
-rw-r--r--gcc/config/mips/mips.c4
-rw-r--r--gcc/config/mips/mips.h2
-rw-r--r--gcc/config/mips/mips.md34
-rw-r--r--gcc/testsuite/ChangeLog5
-rw-r--r--gcc/testsuite/gcc.target/mips/loongson-ctz.c2
-rw-r--r--gcc/testsuite/gcc.target/mips/loongson-dctz.c2
7 files changed, 38 insertions, 22 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index c0aae3a..d2e167b 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,14 @@
+2018-11-07 Chenghua Xu <paul.hua.gm@gmail.com>
+
+ * config/mips/mips.c: Fix typo in documentation of
+ mips_loongson_ext2_prefetch_cookie.
+ (mips_option_override): fix brain twister logical.
+ * config/mips/mips.h: Fix typo in documentation of
+ ISA_HAS_CTZ_CTO and define pattern.
+ * config/mips/mips.md (prefetch): Hoist EXT2 above
+ the 2EF/EXT block.
+ (prefetch_indexed): Hoist EXT2 above the EXT block.
+
2018-11-07 Jan Hubicka <jh@suse.cz>
* tree.c (free_lang_data_in_type): Add fld parameter; simplify
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index 2b83e4e..d78e205 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -15151,7 +15151,7 @@ mips_prefetch_cookie (rtx write, rtx locality)
return GEN_INT (INTVAL (write) + 6);
}
-/* Loongson EXT2 only implements perf hint=0 (prefetch for load) and hint=1
+/* Loongson EXT2 only implements pref hint=0 (prefetch for load) and hint=1
(prefetch for store), other hint just scale to hint = 0 and hint = 1. */
rtx
@@ -20202,7 +20202,7 @@ mips_option_override (void)
is true. If a user explicitly says -mloongson-ext2 -mno-loongson-ext
then that is an error. */
if (!TARGET_LOONGSON_EXT
- && !((target_flags_explicit & MASK_LOONGSON_EXT) == 0))
+ && (target_flags_explicit & MASK_LOONGSON_EXT) != 0)
error ("%<-mloongson-ext2%> must be used with %<-mloongson-ext%>");
target_flags |= MASK_LOONGSON_EXT;
}
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index 0a92cf6..11ca364 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -1158,7 +1158,7 @@ struct mips_cpu_info {
/* ISA has count leading zeroes/ones instruction (not implemented). */
#define ISA_HAS_CLZ_CLO (mips_isa_rev >= 1 && !TARGET_MIPS16)
-/* ISA has count tailing zeroes/ones instruction. */
+/* ISA has count trailing zeroes/ones instruction. */
#define ISA_HAS_CTZ_CTO (TARGET_LOONGSON_EXT2)
/* ISA has three operand multiply instructions that put
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index 9e222dc..0cb0cb8 100644
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -3153,7 +3153,7 @@
;;
;; ...................
;;
-;; Count tailing zeroes.
+;; Count trailing zeroes.
;;
;; ...................
;;
@@ -7157,21 +7157,21 @@
(match_operand 2 "const_int_operand" "n"))]
"ISA_HAS_PREFETCH && TARGET_EXPLICIT_RELOCS"
{
- if (TARGET_LOONGSON_2EF || TARGET_LOONGSON_EXT || TARGET_LOONGSON_EXT2)
+ if (TARGET_LOONGSON_2EF || TARGET_LOONGSON_EXT)
{
- /* Loongson ext2 implementation pref insnstructions. */
- if (TARGET_LOONGSON_EXT2)
- {
- operands[1] = mips_loongson_ext2_prefetch_cookie (operands[1],
- operands[2]);
- return "pref\t%1, %a0";
- }
/* Loongson 2[ef] and Loongson ext use load to $0 for prefetching. */
if (TARGET_64BIT)
return "ld\t$0,%a0";
else
return "lw\t$0,%a0";
}
+ /* Loongson ext2 implementation pref instructions. */
+ if (TARGET_LOONGSON_EXT2)
+ {
+ operands[1] = mips_loongson_ext2_prefetch_cookie (operands[1],
+ operands[2]);
+ return "pref\t%1, %a0";
+ }
operands[1] = mips_prefetch_cookie (operands[1], operands[2]);
return "pref\t%1,%a0";
}
@@ -7184,21 +7184,21 @@
(match_operand 3 "const_int_operand" "n"))]
"ISA_HAS_PREFETCHX && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
{
- if (TARGET_LOONGSON_EXT || TARGET_LOONGSON_EXT2)
+ if (TARGET_LOONGSON_EXT)
{
- /* Loongson ext2 implementation pref insnstructions. */
- if (TARGET_LOONGSON_EXT2)
- {
- operands[2] = mips_loongson_ext2_prefetch_cookie (operands[2],
- operands[3]);
- return "prefx\t%2,%1(%0)";
- }
/* Loongson Loongson ext use index load to $0 for prefetching. */
if (TARGET_64BIT)
return "gsldx\t$0,0(%0,%1)";
else
return "gslwx\t$0,0(%0,%1)";
}
+ /* Loongson ext2 implementation pref instructions. */
+ if (TARGET_LOONGSON_EXT2)
+ {
+ operands[2] = mips_loongson_ext2_prefetch_cookie (operands[2],
+ operands[3]);
+ return "prefx\t%2,%1(%0)";
+ }
operands[2] = mips_prefetch_cookie (operands[2], operands[3]);
return "prefx\t%2,%1(%0)";
}
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 65c1cf1..79e0fa3 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2018-11-07 Chenghua Xu <paul.hua.gm@gmail.com>
+
+ * gcc.target/mips/loongson-ctz.c: Fix typo.
+ * gcc.target/mips/loongson-dctz.c: Fix typo.
+
2018-11-07 Jan Hubicka <jh@suse.cz>
* g++.dg/lto/odr-1_1.C: Fix template.
diff --git a/gcc/testsuite/gcc.target/mips/loongson-ctz.c b/gcc/testsuite/gcc.target/mips/loongson-ctz.c
index 8df66a0..7238fe2 100644
--- a/gcc/testsuite/gcc.target/mips/loongson-ctz.c
+++ b/gcc/testsuite/gcc.target/mips/loongson-ctz.c
@@ -1,4 +1,4 @@
-/* Test cases for Loongson EXT2 instrutions. */
+/* Test cases for Loongson EXT2 instructions. */
/* { dg-do compile } */
/* { dg-options "-mloongson-ext2" } */
diff --git a/gcc/testsuite/gcc.target/mips/loongson-dctz.c b/gcc/testsuite/gcc.target/mips/loongson-dctz.c
index 8c47433..f0c42f8 100644
--- a/gcc/testsuite/gcc.target/mips/loongson-dctz.c
+++ b/gcc/testsuite/gcc.target/mips/loongson-dctz.c
@@ -1,4 +1,4 @@
-/* Test cases for Loongson EXT2 instrutions. */
+/* Test cases for Loongson EXT2 instructions. */
/* { dg-do compile } */
/* { dg-options "-mloongson-ext2" } */