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| author | Kyrylo Tkachov <kyrylo.tkachov@arm.com> | 2018-11-07 17:55:27 +0000 |
|---|---|---|
| committer | Kyrylo Tkachov <ktkachov@gcc.gnu.org> | 2018-11-07 17:55:27 +0000 |
| commit | ce1485c1f7b8da3aa1f4177c92ae8e6af2fb4a3d (patch) | |
| tree | d77698ae8f4a2363a80f40e196041a58062e99c0 | |
| parent | 72a7649aa53aa210bbe0d89f1ee083f7fcfc61d6 (diff) | |
| download | gcc-ce1485c1f7b8da3aa1f4177c92ae8e6af2fb4a3d.zip gcc-ce1485c1f7b8da3aa1f4177c92ae8e6af2fb4a3d.tar.gz gcc-ce1485c1f7b8da3aa1f4177c92ae8e6af2fb4a3d.tar.bz2 | |
[AArch64] Add -mcpu/-mtune support for Arm Ares
This adds support for the Arm Ares CPU for AArch64.
It implements the Armv8.2-A architecture with the optional features
of statistical profiling, dot product and FP16 on by default.
Note: Ares is a codename to enable early adopters and in time
we will add the final product name once it's announced.
* config/aarch64/aarch64-cores.def (ares): Define.
* config/aarch64/aarch64-tune.md: Regenerate.
* doc/invoke.texi (AArch64 Options): Document ares value for mtune.
From-SVN: r265880
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64-cores.def | 1 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64-tune.md | 2 | ||||
| -rw-r--r-- | gcc/doc/invoke.texi | 14 |
4 files changed, 15 insertions, 8 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 3a9f6ea..4cef615 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2018-11-07 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + + * config/aarch64/aarch64-cores.def (ares): Define. + * config/aarch64/aarch64-tune.md: Regenerate. + * doc/invoke.texi (AArch64 Options): Document ares value for mtune. + 2018-11-07 Jan Hubicka <jh@suse.cz> * tree.c (fld_incomplete_type_of): Clear TREE_ADDRESSABLE. diff --git a/gcc/config/aarch64/aarch64-cores.def b/gcc/config/aarch64/aarch64-cores.def index de1a998b..1f3ac56 100644 --- a/gcc/config/aarch64/aarch64-cores.def +++ b/gcc/config/aarch64/aarch64-cores.def @@ -89,6 +89,7 @@ AARCH64_CORE("thunderx2t99", thunderx2t99, thunderx2t99, 8_1A, AARCH64_FL_FOR AARCH64_CORE("cortex-a55", cortexa55, cortexa53, 8_2A, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD, cortexa53, 0x41, 0xd05, -1) AARCH64_CORE("cortex-a75", cortexa75, cortexa57, 8_2A, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD, cortexa73, 0x41, 0xd0a, -1) AARCH64_CORE("cortex-a76", cortexa76, cortexa57, 8_2A, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD, cortexa72, 0x41, 0xd0b, -1) +AARCH64_CORE("ares", ares, cortexa57, 8_2A, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD | AARCH64_FL_PROFILE, cortexa72, 0x41, 0xd0c, -1) /* ARMv8.4-A Architecture Processors. */ diff --git a/gcc/config/aarch64/aarch64-tune.md b/gcc/config/aarch64/aarch64-tune.md index ad52d89d..fade1d4 100644 --- a/gcc/config/aarch64/aarch64-tune.md +++ b/gcc/config/aarch64/aarch64-tune.md @@ -1,5 +1,5 @@ ;; -*- buffer-read-only: t -*- ;; Generated automatically by gentune.sh from aarch64-cores.def (define_attr "tune" - "cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thunderx,thunderxt88p1,thunderxt88,thunderxt81,thunderxt83,xgene1,falkor,qdf24xx,exynosm1,phecda,thunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa75,cortexa76,tsv110,saphira,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,cortexa75cortexa55,cortexa76cortexa55" + "cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thunderx,thunderxt88p1,thunderxt88,thunderxt81,thunderxt83,xgene1,falkor,qdf24xx,exynosm1,phecda,thunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa75,cortexa76,ares,tsv110,saphira,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,cortexa75cortexa55,cortexa76cortexa55" (const (symbol_ref "((enum attr_tune) aarch64_tune)"))) diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index ae260c6..48c9706 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -15157,13 +15157,13 @@ Specify the name of the target processor for which GCC should tune the performance of the code. Permissible values for this option are: @samp{generic}, @samp{cortex-a35}, @samp{cortex-a53}, @samp{cortex-a55}, @samp{cortex-a57}, @samp{cortex-a72}, @samp{cortex-a73}, @samp{cortex-a75}, -@samp{cortex-a76}, @samp{exynos-m1}, @samp{falkor}, @samp{qdf24xx}, -@samp{saphira}, @samp{phecda}, @samp{xgene1}, @samp{vulcan}, @samp{thunderx}, -@samp{thunderxt88}, @samp{thunderxt88p1}, @samp{thunderxt81},@samp{tsv110}, -@samp{thunderxt83}, @samp{thunderx2t99}, @samp{cortex-a57.cortex-a53}, -@samp{cortex-a72.cortex-a53}, @samp{cortex-a73.cortex-a35}, -@samp{cortex-a73.cortex-a53}, @samp{cortex-a75.cortex-a55}, -@samp{cortex-a76.cortex-a55} +@samp{cortex-a76}, @samp{ares}, @samp{exynos-m1}, @samp{falkor}, +@samp{qdf24xx}, @samp{saphira}, @samp{phecda}, @samp{xgene1}, @samp{vulcan}, +@samp{thunderx}, @samp{thunderxt88}, @samp{thunderxt88p1}, @samp{thunderxt81}, +@samp{tsv110}, @samp{thunderxt83}, @samp{thunderx2t99}, +@samp{cortex-a57.cortex-a53}, @samp{cortex-a72.cortex-a53}, +@samp{cortex-a73.cortex-a35}, @samp{cortex-a73.cortex-a53}, +@samp{cortex-a75.cortex-a55}, @samp{cortex-a76.cortex-a55} @samp{native}. The values @samp{cortex-a57.cortex-a53}, @samp{cortex-a72.cortex-a53}, |