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| author | Michael Meissner <meissner@gcc.gnu.org> | 2020-02-06 18:39:48 -0500 |
|---|---|---|
| committer | Michael Meissner <meissner@gcc.gnu.org> | 2020-02-06 18:39:48 -0500 |
| commit | a66219dce7fcba068a0998dd926e2ffc6857f149 (patch) | |
| tree | de97619bb0275643467e5028ec4536ba9bac4030 | |
| parent | d26f37a16e3ed3d75a93ffb1da10c44c36a8a36d (diff) | |
| download | gcc-a66219dce7fcba068a0998dd926e2ffc6857f149.zip gcc-a66219dce7fcba068a0998dd926e2ffc6857f149.tar.gz gcc-a66219dce7fcba068a0998dd926e2ffc6857f149.tar.bz2 | |
Fix PR 93569.
2020-02-06 Michael Meissner <meissner@linux.ibm.com>
PR target/93569
* config/rs6000/rs6000.c (reg_to_non_prefixed): Before ISA 3.0
we only had X-FORM (reg+reg) addressing for vectors. Also before
ISA 3.0, we only had X-FORM addressing for scalars in the
traditional Altivec registers.
| -rw-r--r-- | gcc/ChangeLog | 8 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000.c | 11 |
2 files changed, 16 insertions, 3 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index aec58a0..9797dd4 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2020-02-06 Michael Meissner <meissner@linux.ibm.com> + + PR target/93569 + * config/rs6000/rs6000.c (reg_to_non_prefixed): Before ISA 3.0 + we only had X-FORM (reg+reg) addressing for vectors. Also before + ISA 3.0, we only had X-FORM addressing for scalars in the + traditional Altivec registers. + 2020-02-06 <zhongyunde@huawei.com> Vladimir Makarov <vmakarov@redhat.com> diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index f2516a8..fc68976 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -24932,7 +24932,8 @@ reg_to_non_prefixed (rtx reg, machine_mode mode) unsigned size = GET_MODE_SIZE (mode); /* FPR registers use D-mode for scalars, and DQ-mode for vectors, IEEE - 128-bit floating point, and 128-bit integers. */ + 128-bit floating point, and 128-bit integers. Before power9, only indexed + addressing was available for vectors. */ if (FP_REGNO_P (r)) { if (mode == SFmode || size == 8 || FLOAT128_2REG_P (mode)) @@ -24945,16 +24946,20 @@ reg_to_non_prefixed (rtx reg, machine_mode mode) && (VECTOR_MODE_P (mode) || FLOAT128_VECTOR_P (mode) || mode == TImode || mode == CTImode)) - return NON_PREFIXED_DQ; + return (TARGET_P9_VECTOR) ? NON_PREFIXED_DQ : NON_PREFIXED_X; else return NON_PREFIXED_DEFAULT; } /* Altivec registers use DS-mode for scalars, and DQ-mode for vectors, IEEE - 128-bit floating point, and 128-bit integers. */ + 128-bit floating point, and 128-bit integers. Before power9, only indexed + addressing was available. */ else if (ALTIVEC_REGNO_P (r)) { + if (!TARGET_P9_VECTOR) + return NON_PREFIXED_X; + if (mode == SFmode || size == 8 || FLOAT128_2REG_P (mode)) return NON_PREFIXED_DS; |