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| author | Kito Cheng <kito.cheng@gmail.com> | 2017-11-03 14:59:39 +0000 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@gcc.gnu.org> | 2017-11-03 14:59:39 +0000 |
| commit | 13e4f305e040097de34481a72756dbe0ebd06dbc (patch) | |
| tree | 380cb8477c0497c3cb8875e96f58d583c6d36033 | |
| parent | 91afdf4c797b1768036b2e32728482c2139e05e1 (diff) | |
| download | gcc-13e4f305e040097de34481a72756dbe0ebd06dbc.zip gcc-13e4f305e040097de34481a72756dbe0ebd06dbc.tar.gz gcc-13e4f305e040097de34481a72756dbe0ebd06dbc.tar.bz2 | |
RISC-V: Handle non-legitimate address in riscv_legitimize_move
GCC may generate non-legitimate address due to we allow some
load/store with non-legitimate address in pic.md.
gcc/ChangeLog
2017-11-03 Kito Cheng <kito.cheng@gmail.com>
* config/riscv/riscv.c (riscv_legitimize_move): Handle
non-legitimate address.
From-SVN: r254376
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/riscv/riscv.c | 16 |
2 files changed, 21 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 561e3da..bbfdfe2 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2017-11-03 Kito Cheng <kito.cheng@gmail.com> + + * config/riscv/riscv.c (riscv_legitimize_move): Handle + non-legitimate address. + 2017-11-03 Segher Boessenkool <segher@kernel.crashing.org> * config/rs6000/rs6000.md (*lt0_disi): Delete. diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c index c34468e..b81a2d2 100644 --- a/gcc/config/riscv/riscv.c +++ b/gcc/config/riscv/riscv.c @@ -1332,6 +1332,22 @@ riscv_legitimize_move (machine_mode mode, rtx dest, rtx src) return true; } + /* RISC-V GCC may generate non-legitimate address due to we provide some + pattern for optimize access PIC local symbol and it's make GCC generate + unrecognizable instruction during optmizing. */ + + if (MEM_P (dest) && !riscv_legitimate_address_p (mode, XEXP (dest, 0), + reload_completed)) + { + XEXP (dest, 0) = riscv_force_address (XEXP (dest, 0), mode); + } + + if (MEM_P (src) && !riscv_legitimate_address_p (mode, XEXP (src, 0), + reload_completed)) + { + XEXP (src, 0) = riscv_force_address (XEXP (src, 0), mode); + } + return false; } |