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| author | Jeevitha <jeevitha@linux.ibm.com> | 2024-03-07 07:41:38 -0600 |
|---|---|---|
| committer | Jeevitha <jeevitha@linux.ibm.com> | 2024-03-07 08:15:20 -0600 |
| commit | fa0468877869f52b05742de6deef582e4dd296fc (patch) | |
| tree | 5ade9877d68e1de346f6d5c16e7e4b3df51e1264 | |
| parent | e71a4e81729516eed8782a255ff37617e6fd4b69 (diff) | |
| download | gcc-fa0468877869f52b05742de6deef582e4dd296fc.zip gcc-fa0468877869f52b05742de6deef582e4dd296fc.tar.gz gcc-fa0468877869f52b05742de6deef582e4dd296fc.tar.bz2 | |
rs6000: Don't ICE when compiling the __builtin_vsx_splat_2di [PR113950]
When we expand the __builtin_vsx_splat_2di built-in, we were allowing immediate
value for second operand which causes an unrecognizable insn ICE. Even though
the immediate value was forced into a register, it wasn't correctly assigned
to the second operand. So corrected the assignment of op1 to operands[1].
2024-03-07 Jeevitha Palanisamy <jeevitha@linux.ibm.com>
gcc/
PR target/113950
* config/rs6000/vsx.md (vsx_splat_<mode>): Correct assignment to operand1
and simplify else if with else.
gcc/testsuite/
PR target/113950
* gcc.target/powerpc/pr113950.c: New testcase.
| -rw-r--r-- | gcc/config/rs6000/vsx.md | 4 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/powerpc/pr113950.c | 24 |
2 files changed, 26 insertions, 2 deletions
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 6111cc9..f135fa0 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -4666,8 +4666,8 @@ rtx op1 = operands[1]; if (MEM_P (op1)) operands[1] = rs6000_force_indexed_or_indirect_mem (op1); - else if (!REG_P (op1)) - op1 = force_reg (<VSX_D:VEC_base>mode, op1); + else + operands[1] = force_reg (<VSX_D:VEC_base>mode, op1); }) (define_insn "vsx_splat_<mode>_reg" diff --git a/gcc/testsuite/gcc.target/powerpc/pr113950.c b/gcc/testsuite/gcc.target/powerpc/pr113950.c new file mode 100644 index 0000000..359963d --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr113950.c @@ -0,0 +1,24 @@ +/* PR target/113950 */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mvsx" } */ + +/* Verify we do not ICE on the following. */ + +void abort (void); + +int main () +{ + int i; + vector signed long long vsll_result, vsll_expected_result; + signed long long sll_arg1; + + sll_arg1 = 300; + vsll_expected_result = (vector signed long long) {300, 300}; + vsll_result = __builtin_vsx_splat_2di (sll_arg1); + + for (i = 0; i < 2; i++) + if (vsll_result[i] != vsll_expected_result[i]) + abort(); + + return 0; +} |