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| author | Andrew Pinski <quic_apinski@quicinc.com> | 2024-07-22 16:18:47 -0700 |
|---|---|---|
| committer | Thomas Koenig <tkoenig@gcc.gnu.org> | 2024-07-28 19:06:01 +0200 |
| commit | ecbfaf0056d5932634e0bf15c60d2790a77f7016 (patch) | |
| tree | 35301898be6e18d1f19c58386c4417389620b02b | |
| parent | fe2e945c18752903d8db4118ef033d606525dc83 (diff) | |
| download | gcc-ecbfaf0056d5932634e0bf15c60d2790a77f7016.zip gcc-ecbfaf0056d5932634e0bf15c60d2790a77f7016.tar.gz gcc-ecbfaf0056d5932634e0bf15c60d2790a77f7016.tar.bz2 | |
aarch64: Use iorn and andn standard pattern names for scalar modes
Since r15-1890-gf379596e0ba99d, these are the new optabs.
So let's use these names for them. These will be used to
generate during expand from gimple in the next few patches.
Built and tested for aarch64-linux-gnu with no regressions.
gcc/ChangeLog:
* config/aarch64/aarch64.md (*<NLOGICAL:optab>_one_cmpl<mode>3): Rename to ...
(<NLOGICAL:optab>n<mode>3): This.
(*<NLOGICAL:optab>_one_cmplsidi3_ze): Rename to ...
(*<NLOGICAL:optab>nsidi3_ze): This.
Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
| -rw-r--r-- | gcc/config/aarch64/aarch64.md | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 94ff0ee..ed29127 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -5069,18 +5069,18 @@ ;; Binary logical operators negating one operand, i.e. (a & !b), (a | !b). -(define_insn "*<NLOGICAL:optab>_one_cmpl<mode>3" +(define_insn "<NLOGICAL:optab>n<mode>3" [(set (match_operand:GPI 0 "register_operand") - (NLOGICAL:GPI (not:GPI (match_operand:GPI 1 "register_operand")) - (match_operand:GPI 2 "register_operand")))] + (NLOGICAL:GPI (not:GPI (match_operand:GPI 2 "register_operand")) + (match_operand:GPI 1 "register_operand")))] "" {@ [ cons: =0 , 1 , 2 ; attrs: type , arch ] - [ r , r , r ; logic_reg , * ] <NLOGICAL:nlogical>\t%<w>0, %<w>2, %<w>1 - [ w , w , w ; neon_logic , simd ] <NLOGICAL:nlogical>\t%0.<Vbtype>, %2.<Vbtype>, %1.<Vbtype> + [ r , r , r ; logic_reg , * ] <NLOGICAL:nlogical>\t%<w>0, %<w>1, %<w>2 + [ w , w , w ; neon_logic , simd ] <NLOGICAL:nlogical>\t%0.<Vbtype>, %1.<Vbtype>, %2.<Vbtype> } ) -(define_insn "*<NLOGICAL:optab>_one_cmplsidi3_ze" +(define_insn "*<NLOGICAL:optab>nsidi3_ze" [(set (match_operand:DI 0 "register_operand" "=r") (zero_extend:DI (NLOGICAL:SI (not:SI (match_operand:SI 1 "register_operand" "r")) |