RISC-V: Disable AVL propagation of slidedown instructions

Re-check again RVV ISA, I find that we can't allow AVL propagation not only
for vrgather, but also slidedown instructions.

Committed.

	PR target/112599

gcc/ChangeLog:

	* config/riscv/riscv-avlprop.cc (avl_can_be_propagated_p): Add slidedown.
	(vlmax_ta_p): Ditto.
	(pass_avlprop::get_vlmax_ta_preferred_avl): Ditto.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/vf_avl-1.c: Adapt test.
	* gcc.target/riscv/rvv/autovec/pr112599-3.c: New test.

3 files changed, 35 insertions, 7 deletions

diff --git a/gcc/config/riscv/riscv-avlprop.cc b/gcc/config/riscv/riscv-avlprop.cc
index 7a741c2..d298f0e 100644
--- a/gcc/config/riscv/riscv-avlprop.cc
+++ b/gcc/config/riscv/riscv-avlprop.cc
@@ -108,17 +108,29 @@ avlprop_type_to_str (enum avlprop_type type)
 static bool
 avl_can_be_propagated_p (rtx_insn *rinsn)
 {
-  /* The index of "vrgather dest, source, index" may pick up the
-     element which has index >= AVL, so we can't strip the elements
-     that has index >= AVL of source register.  */
-  return get_attr_type (rinsn) != TYPE_VGATHER;
+  /* We can't do AVL propagation when the instruction is potentially
+     touching the element with i > AVL.  So, we don't do AVL propagation
+     on these following situations:
+
+       - The index of "vrgather dest, source, index" may pick up the
+	 element which has index >= AVL, so we can't strip the elements
+	 that has index >= AVL of source register.
+       - The last element of vslide1down is AVL + 1 according to RVV ISA:
+	 vstart <= i < vl-1    vd[i] = vs2[i+1] if v0.mask[i] enabled
+       - The last multiple elements of vslidedown can be the element
+	 has index >= AVL according to RVV ISA:
+	 0 <= i+OFFSET < VLMAX   src[i] = vs2[i+OFFSET]
+	 vstart <= i < vl vd[i] = src[i] if v0.mask[i] enabled.  */
+  return get_attr_type (rinsn) != TYPE_VGATHER
+	 && get_attr_type (rinsn) != TYPE_VSLIDEDOWN
+	 && get_attr_type (rinsn) != TYPE_VISLIDE1DOWN
+	 && get_attr_type (rinsn) != TYPE_VFSLIDE1DOWN;
 }
 
 static bool
 vlmax_ta_p (rtx_insn *rinsn)
 {
-  return vlmax_avl_type_p (rinsn) && tail_agnostic_p (rinsn)
-	 && avl_can_be_propagated_p (rinsn);
+  return vlmax_avl_type_p (rinsn) && tail_agnostic_p (rinsn);
 }
 
 static machine_mode
@@ -271,6 +283,8 @@ pass_avlprop::get_preferred_avl (
 rtx
 pass_avlprop::get_vlmax_ta_preferred_avl (insn_info *insn) const
 {
+  if (!avl_can_be_propagated_p (insn->rtl ()))
+    return NULL_RTX;
   int sew = get_sew (insn->rtl ());
   enum vlmul_type vlmul = get_vlmul (insn->rtl ());
   int ratio = calculate_ratio (sew, vlmul);
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112599-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112599-3.c
new file mode 100644
index 0000000..0954fe2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112599-3.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zfh_zvl1024b -mabi=lp64d -O3 --param=riscv-autovec-preference=fixed-vlmax" } */
+
+#include "riscv_vector.h"
+
+typedef int64_t v1024b __attribute__ ((vector_size (128)));
+
+void foo (void *out, void *in, int64_t a, int64_t b, int64_t c, int64_t d, int64_t e)
+{
+  v1024b v = {a,a,a,a,a,a,a,a,a,a,a,a,b,c,d,e};
+  __riscv_vse64_v_i64m1 (out, (vint64m1_t)v, 12);
+}
+
+/* { dg-final { scan-assembler {vsetivli\s+zero,\s*16} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-1.c
index 11adf6b..8f352db 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-1.c
@@ -12,4 +12,4 @@ f_vnx2qi (int8_t a, int8_t b, int8_t *out)
   *(vnx2qi *) out = v;
 }
 
-/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*2,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 } } */
+/* { dg-final { scan-assembler {vsetivli\s+zero,\s*2,\s*e8,\s*mf8,\s*t[au],\s*m[au]} } } */