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authorHongyu Wang <hongyu.wang@intel.com>2023-08-24 14:41:42 +0800
committerHongyu Wang <hongyu.wang@intel.com>2023-08-25 08:46:10 +0800
commite62fe74e5af913079ba296c74759cd74c0759e8e (patch)
treecf47c2c2873dbbb536489670825eb88d93f63a22
parent6d47c9b418295b2da14577a108bc4c9a0c7f16cf (diff)
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Fix avx512ne2ps2bf16 wrong code [PR 111127]
Correct the parameter order for avx512ne2ps2bf16_maskz expander gcc/ChangeLog: PR target/111127 * config/i386/sse.md (avx512f_cvtne2ps2bf16_<mode>_maskz): Adjust paramter order. gcc/testsuite/ChangeLog: PR target/111127 * gcc.target/i386/pr111127.c: New test.
-rw-r--r--gcc/config/i386/sse.md4
-rw-r--r--gcc/testsuite/gcc.target/i386/pr111127.c24
2 files changed, 26 insertions, 2 deletions
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 59a0eb1..2b1f351 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -29955,8 +29955,8 @@
(match_operand:<avx512fmaskmode> 3 "register_operand")]
"TARGET_AVX512BF16"
{
- emit_insn (gen_avx512f_cvtne2ps2bf16_<mode>_mask(operands[0], operands[2],
- operands[1], CONST0_RTX(<MODE>mode), operands[3]));
+ emit_insn (gen_avx512f_cvtne2ps2bf16_<mode>_mask(operands[0], operands[1],
+ operands[2], CONST0_RTX(<MODE>mode), operands[3]));
DONE;
})
diff --git a/gcc/testsuite/gcc.target/i386/pr111127.c b/gcc/testsuite/gcc.target/i386/pr111127.c
new file mode 100644
index 0000000..c124bc1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr111127.c
@@ -0,0 +1,24 @@
+/* PR target/111127 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx512bf16 -mavx512vl" } */
+/* { dg-final { scan-assembler-times "vcvtne2ps2bf16\[ \\t\]+\[^\{\n\]*%zmm1, %zmm0, %zmm0\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtne2ps2bf16\[ \\t\]+\[^\{\n\]*%ymm1, %ymm0, %ymm0\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtne2ps2bf16\[ \\t\]+\[^\{\n\]*%xmm1, %xmm0, %xmm0\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */
+
+#include <immintrin.h>
+
+__m512bh cvttest(__mmask32 k, __m512 a, __m512 b)
+{
+ return _mm512_maskz_cvtne2ps_pbh (k,a,b);
+}
+
+__m256bh cvttest2(__mmask16 k, __m256 a, __m256 b)
+{
+ return _mm256_maskz_cvtne2ps_pbh (k,a,b);
+}
+
+__m128bh cvttest3(__mmask8 k, __m128 a, __m128 b)
+{
+ return _mm_maskz_cvtne2ps_pbh (k,a,b);
+}
+