diff options
| author | Olga Golovanevsky <olga@il.ibm.com> | 2004-03-28 15:07:21 +0000 |
|---|---|---|
| committer | Dorit Nuzman <dorit@gcc.gnu.org> | 2004-03-28 15:07:21 +0000 |
| commit | e20f3dd1437fad78e3142fe4834773b71c1b100c (patch) | |
| tree | eaaf7e754125a89e203c506d2b55c80f02d64999 | |
| parent | d5ebbf584f8f98fb0a84c2de19d62bfbd3c363cc (diff) | |
| download | gcc-e20f3dd1437fad78e3142fe4834773b71c1b100c.zip gcc-e20f3dd1437fad78e3142fe4834773b71c1b100c.tar.gz gcc-e20f3dd1437fad78e3142fe4834773b71c1b100c.tar.bz2 | |
altivec.md: (andvv16qi3...
* config/rs6000/altivec.md: (andvv16qi3, andv8hi3, one_cmplv16qi2,
one_cmplv8hi2, one_cmplv4si2, iorv16qi3, iorv8hi3,): New modelling.
Co-Authored-By: Dorit Naishlos <dorit@il.ibm.com>
From-SVN: r80039
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/rs6000/altivec.md | 53 |
2 files changed, 59 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 281ab22..bb64ccc 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2004-03-28 Olga Golovonevsky <olga@il.ibm.com> + Dorit Naishlos <dorit@il.ibm.com> + + * config/rs6000/altivec.md: (andvv16qi3, andv8hi3, one_cmplv16qi2, + one_cmplv8hi2, one_cmplv4si2, iorv16qi3, iorv8hi3,): New modelling. + 2004-03-28 Stephane Carrez <stcarrez@nerim.fr> * config/m68hc11/m68hc11-protos.h (m68hc11_page0_symbol_p): Declare. diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index 2ede79d..684a5d4 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -388,6 +388,22 @@ "vaddsws %0,%1,%2" [(set_attr "type" "vecsimple")]) +(define_insn "andv16qi3" + [(set (match_operand:V16QI 0 "register_operand" "=v") + (and:V16QI (match_operand:V16QI 1 "register_operand" "v") + (match_operand:V16QI 2 "register_operand" "v")))] + "TARGET_ALTIVEC" + "vand %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +(define_insn "andv8hi3" + [(set (match_operand:V8HI 0 "register_operand" "=v") + (and:V8HI (match_operand:V8HI 1 "register_operand" "v") + (match_operand:V8HI 2 "register_operand" "v")))] + "TARGET_ALTIVEC" + "vand %0,%1,%2" + [(set_attr "type" "vecsimple")]) + (define_insn "andv4si3" [(set (match_operand:V4SI 0 "register_operand" "=v") (and:V4SI (match_operand:V4SI 1 "register_operand" "v") @@ -975,6 +991,43 @@ "TARGET_ALTIVEC" "vnor %0,%1,%2" [(set_attr "type" "vecsimple")]) + +(define_insn "one_cmplv16qi2" + [(set (match_operand:V16QI 0 "register_operand" "=v") + (not:V16QI (match_operand:V16QI 1 "register_operand" "v")))] + "TARGET_ALTIVEC" + "vnot %0,%1" + [(set_attr "type" "vecsimple")]) + +(define_insn "one_cmplv8hi2" + [(set (match_operand:V8HI 0 "register_operand" "=v") + (not:V8HI (match_operand:V8HI 1 "register_operand" "v")))] + "TARGET_ALTIVEC" + "vnot %0,%1" + [(set_attr "type" "vecsimple")]) + +(define_insn "one_cmplv4si2" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (not:V4SI (match_operand:V4SI 1 "register_operand" "v")))] + "TARGET_ALTIVEC" + "vnot %0,%1" + [(set_attr "type" "vecsimple")]) + +(define_insn "iorv16qi3" + [(set (match_operand:V16QI 0 "register_operand" "=v") + (ior:V16QI (match_operand:V16QI 1 "register_operand" "v") + (match_operand:V16QI 2 "register_operand" "v")))] + "TARGET_ALTIVEC" + "vor %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +(define_insn "iorv8hi3" + [(set (match_operand:V8HI 0 "register_operand" "=v") + (ior:V8HI (match_operand:V8HI 1 "register_operand" "v") + (match_operand:V8HI 2 "register_operand" "v")))] + "TARGET_ALTIVEC" + "vor %0,%1,%2" + [(set_attr "type" "vecsimple")]) (define_insn "iorv4si3" [(set (match_operand:V4SI 0 "register_operand" "=v") |