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| author | Kyrylo Tkachov <kyrylo.tkachov@arm.com> | 2018-04-20 16:31:19 +0000 |
|---|---|---|
| committer | Kyrylo Tkachov <ktkachov@gcc.gnu.org> | 2018-04-20 16:31:19 +0000 |
| commit | db994ead877220f9f71932b1e16b4945b06aafbd (patch) | |
| tree | f36068fe4ccb38398bc4099a1674c7d8b819433c | |
| parent | a3b82e156de228bbd33c87999f1fbdd519140734 (diff) | |
| download | gcc-db994ead877220f9f71932b1e16b4945b06aafbd.zip gcc-db994ead877220f9f71932b1e16b4945b06aafbd.tar.gz gcc-db994ead877220f9f71932b1e16b4945b06aafbd.tar.bz2 | |
PR testsuite/85483: Move aarch64/sve/vcond_1.c test to g++.dg/other/
I totally botched up this sve test file in 259437.
It needs C++, so move it to g++.dg/other and make it a .C file.
Also adds the target guards to prevent it from running on non-aarch64 targets.
Tested that it passes on aarch64-none-elf and doesn't get run on arm-none-eabi.
Committing to trunk as obvious.
PR testsuite/85483
* gcc.target/aarch64/sve/vcond_1.c: Move to...
* g++.dg/other/sve_vcond_1.C: ... Here. Add target directives.
* gcc.target/aarch64/sve/vcond_1_run.c: Move to...
* g++.dg/other/sve_vcond_1_run.C: ... Here. Change include file name.
From-SVN: r259526
| -rw-r--r-- | gcc/testsuite/ChangeLog | 8 | ||||
| -rw-r--r-- | gcc/testsuite/g++.dg/other/sve_vcond_1.C (renamed from gcc/testsuite/gcc.target/aarch64/sve/vcond_1.c) | 4 | ||||
| -rw-r--r-- | gcc/testsuite/g++.dg/other/sve_vcond_1_run.C (renamed from gcc/testsuite/gcc.target/aarch64/sve/vcond_1_run.c) | 2 |
3 files changed, 11 insertions, 3 deletions
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 8e97876..4bc9301 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,11 @@ +2018-04-20 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + + PR testsuite/85483 + * gcc.target/aarch64/sve/vcond_1.c: Move to... + * g++.dg/other/sve_vcond_1.C: ... Here. Add target directives. + * gcc.target/aarch64/sve/vcond_1_run.c: Move to... + * g++.dg/other/sve_vcond_1_run.C: ... Here. Change include file name. + 2018-04-20 H.J. Lu <hongjiu.lu@intel.com> PR target/85469 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/vcond_1.c b/gcc/testsuite/g++.dg/other/sve_vcond_1.C index 6620842..c1ad0b9 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/vcond_1.c +++ b/gcc/testsuite/g++.dg/other/sve_vcond_1.C @@ -1,5 +1,5 @@ -/* { dg-do assemble { target aarch64_asm_sve_ok } } */ -/* { dg-options "-O -msve-vector-bits=256 --save-temps" } */ +/* { dg-do assemble { target { aarch64_asm_sve_ok && { ! ilp32 } } } } */ +/* { dg-options "-march=armv8.2-a+sve -O -msve-vector-bits=256 --save-temps" } */ typedef __INT8_TYPE__ vnx16qi __attribute__((vector_size(32))); typedef __INT16_TYPE__ vnx8hi __attribute__((vector_size(32))); diff --git a/gcc/testsuite/gcc.target/aarch64/sve/vcond_1_run.c b/gcc/testsuite/g++.dg/other/sve_vcond_1_run.C index 72dab39..d01745e 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/vcond_1_run.c +++ b/gcc/testsuite/g++.dg/other/sve_vcond_1_run.C @@ -2,7 +2,7 @@ /* { dg-options "-O" } */ /* { dg-options "-O -msve-vector-bits=256" { target aarch64_sve256_hw } } */ -#include "vcond_1.c" +#include "sve_vcond_1.c" #define NUM_ELEMS(X) (sizeof (X) / sizeof (X[0])) |