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| author | Alex Coplan <alex.coplan@arm.com> | 2020-09-23 15:21:00 +0100 |
|---|---|---|
| committer | Alex Coplan <alex.coplan@arm.com> | 2020-09-23 15:21:00 +0100 |
| commit | da13b7737662da11f8fefb28eaf4ed7c50c51767 (patch) | |
| tree | b3b48e8ca46af7e6ed501c8aeb5ec43034f94978 | |
| parent | c9d56eb777552ac5ee0c281e1f6e34b6fe929b77 (diff) | |
| download | gcc-da13b7737662da11f8fefb28eaf4ed7c50c51767.zip gcc-da13b7737662da11f8fefb28eaf4ed7c50c51767.tar.gz gcc-da13b7737662da11f8fefb28eaf4ed7c50c51767.tar.bz2 | |
arm: Add support for Neoverse V1 CPU
This adds support for Arm's Neoverse V1 CPU to the AArch32 backend.
---
gcc/ChangeLog:
* config/arm/arm-cpus.in (neoverse-v1): New.
* config/arm/arm-tables.opt: Regenerate.
* config/arm/arm-tune.md: Regenerate.
* doc/invoke.texi: Document support for Neoverse V1.
| -rw-r--r-- | gcc/config/arm/arm-cpus.in | 10 | ||||
| -rw-r--r-- | gcc/config/arm/arm-tables.opt | 3 | ||||
| -rw-r--r-- | gcc/config/arm/arm-tune.md | 4 | ||||
| -rw-r--r-- | gcc/doc/invoke.texi | 6 |
4 files changed, 18 insertions, 5 deletions
diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in index c98f8ed..4550694 100644 --- a/gcc/config/arm/arm-cpus.in +++ b/gcc/config/arm/arm-cpus.in @@ -1478,6 +1478,16 @@ begin cpu cortex-a76.cortex-a55 costs cortex_a57 end cpu cortex-a76.cortex-a55 +# Armv8.4 A-profile Architecture Processors +begin cpu neoverse-v1 + cname neoversev1 + tune for cortex-a57 + tune flags LDSCHED + architecture armv8.4-a+bf16+i8mm + option crypto add FP_ARMv8 CRYPTO + costs cortex_a57 +end cpu neoverse-v1 + # V8 M-profile implementations. begin cpu cortex-m23 cname cortexm23 diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt index ce35661..1a7c319 100644 --- a/gcc/config/arm/arm-tables.opt +++ b/gcc/config/arm/arm-tables.opt @@ -250,6 +250,9 @@ EnumValue Enum(processor_type) String(cortex-a76.cortex-a55) Value( TARGET_CPU_cortexa76cortexa55) EnumValue +Enum(processor_type) String(neoverse-v1) Value( TARGET_CPU_neoversev1) + +EnumValue Enum(processor_type) String(cortex-m23) Value( TARGET_CPU_cortexm23) EnumValue diff --git a/gcc/config/arm/arm-tune.md b/gcc/config/arm/arm-tune.md index 8ea9435..3874f42 100644 --- a/gcc/config/arm/arm-tune.md +++ b/gcc/config/arm/arm-tune.md @@ -46,6 +46,6 @@ cortexa73cortexa53,cortexa55,cortexa75, cortexa76,cortexa76ae,cortexa77, neoversen1,cortexa75cortexa55,cortexa76cortexa55, - cortexm23,cortexm33,cortexm35p, - cortexm55,cortexr52" + neoversev1,cortexm23,cortexm33, + cortexm35p,cortexm55,cortexr52" (const (symbol_ref "((enum attr_tune) arm_tune)"))) diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 1380146..c17e5c6 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -19353,9 +19353,9 @@ Permissible names are: @samp{arm7tdmi}, @samp{arm7tdmi-s}, @samp{arm710t}, @samp{cortex-m35p}, @samp{cortex-m55}, @samp{cortex-m1.small-multiply}, @samp{cortex-m0.small-multiply}, @samp{cortex-m0plus.small-multiply}, @samp{exynos-m1}, @samp{marvell-pj4}, -@samp{neoverse-n1}, @samp{xscale}, @samp{iwmmxt}, @samp{iwmmxt2}, -@samp{ep9312}, @samp{fa526}, @samp{fa626}, @samp{fa606te}, @samp{fa626te}, -@samp{fmp626}, @samp{fa726te}, @samp{xgene1}. +@samp{neoverse-n1}, @samp{neoverse-v1}, @samp{xscale}, @samp{iwmmxt}, +@samp{iwmmxt2}, @samp{ep9312}, @samp{fa526}, @samp{fa626}, @samp{fa606te}, +@samp{fa626te}, @samp{fmp626}, @samp{fa726te}, @samp{xgene1}. Additionally, this option can specify that GCC should tune the performance of the code for a big.LITTLE system. Permissible names are: |