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author | Aldy Hernandez <aldyh@redhat.com> | 2004-05-04 02:24:51 +0000 |
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committer | Aldy Hernandez <aldyh@gcc.gnu.org> | 2004-05-04 02:24:51 +0000 |
commit | d8ecbcdb20d121ca465970e86bec702116163de9 (patch) | |
tree | 024cb84c1af87981445ed879127e8a3b4f1d3b94 | |
parent | 2f7e5a0df0c1766d3b1ed6c1a5c6a0b17f68fa94 (diff) | |
download | gcc-d8ecbcdb20d121ca465970e86bec702116163de9.zip gcc-d8ecbcdb20d121ca465970e86bec702116163de9.tar.gz gcc-d8ecbcdb20d121ca465970e86bec702116163de9.tar.bz2 |
rs6000-protos.h: Protoize rs6000_hard_regno_nregs.
* config/rs6000/rs6000-protos.h: Protoize rs6000_hard_regno_nregs.
* config/rs6000/rs6000.c (rs6000_hard_regno_nregs): New.
* config/rs6000/rs6000.h (HARD_REGNO_NREGS): Call
rs6000_hard_regno_nregs.
From-SVN: r81467
-rw-r--r-- | gcc/ChangeLog | 9 | ||||
-rw-r--r-- | gcc/config/rs6000/rs6000-protos.h | 1 | ||||
-rw-r--r-- | gcc/config/rs6000/rs6000.c | 28 | ||||
-rw-r--r-- | gcc/config/rs6000/rs6000.h | 22 |
4 files changed, 41 insertions, 19 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 45179bf..f98f7cd 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,12 @@ +2004-05-03 Aldy Hernandez <aldyh@redhat.com> + + * config/rs6000/rs6000-protos.h: Protoize rs6000_hard_regno_nregs. + + * config/rs6000/rs6000.c (rs6000_hard_regno_nregs): New. + + * config/rs6000/rs6000.h (HARD_REGNO_NREGS): Call + rs6000_hard_regno_nregs. + 2004-05-03 Eric Christopher <echristo@redhat.com> * config/s390/s390.c (s390_emit_prologue): Call unspec tpf diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h index d368033..93ed98a 100644 --- a/gcc/config/rs6000/rs6000-protos.h +++ b/gcc/config/rs6000/rs6000-protos.h @@ -201,6 +201,7 @@ extern int rs6000_memory_move_cost (enum machine_mode, enum reg_class, int); extern bool rs6000_tls_referenced_p (rtx); extern int rs6000_tls_symbol_ref (rtx, enum machine_mode); extern void rs6000_output_dwarf_dtprel (FILE*, int, rtx); +extern int rs6000_hard_regno_nregs (int, enum machine_mode); /* Declare functions in rs6000-c.c */ diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index c405abd..b188132 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -3343,6 +3343,34 @@ rs6000_mode_dependent_address (rtx addr) return false; } + +/* Return number of consecutive hard regs needed starting at reg REGNO + to hold something of mode MODE. + This is ordinarily the length in words of a value of mode MODE + but can be less for certain modes in special long registers. + + For the SPE, GPRs are 64 bits but only 32 bits are visible in + scalar instructions. The upper 32 bits are only available to the + SIMD instructions. + + POWER and PowerPC GPRs hold 32 bits worth; + PowerPC64 GPRs and FPRs point register holds 64 bits worth. */ + +int +rs6000_hard_regno_nregs (int regno, enum machine_mode mode) +{ + if (FP_REGNO_P (regno)) + return (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD; + + if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode)) + return (GET_MODE_SIZE (mode) + UNITS_PER_SPE_WORD - 1) / UNITS_PER_SPE_WORD; + + if (ALTIVEC_REGNO_P (regno)) + return + (GET_MODE_SIZE (mode) + UNITS_PER_ALTIVEC_WORD - 1) / UNITS_PER_ALTIVEC_WORD; + + return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD; +} /* Try to output insns to set TARGET equal to the constant C if it can be done in less than N insns. Do all computations in MODE. diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index f3d4493..dc57427 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -997,25 +997,9 @@ extern const char *rs6000_warn_altivec_long_switch; #define ALTIVEC_REGNO_P(N) ((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO) /* Return number of consecutive hard regs needed starting at reg REGNO - to hold something of mode MODE. - This is ordinarily the length in words of a value of mode MODE - but can be less for certain modes in special long registers. - - For the SPE, GPRs are 64 bits but only 32 bits are visible in - scalar instructions. The upper 32 bits are only available to the - SIMD instructions. - - POWER and PowerPC GPRs hold 32 bits worth; - PowerPC64 GPRs and FPRs point register holds 64 bits worth. */ - -#define HARD_REGNO_NREGS(REGNO, MODE) \ - (FP_REGNO_P (REGNO) \ - ? ((GET_MODE_SIZE (MODE) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD) \ - : (SPE_SIMD_REGNO_P (REGNO) && TARGET_SPE && SPE_VECTOR_MODE (MODE)) \ - ? ((GET_MODE_SIZE (MODE) + UNITS_PER_SPE_WORD - 1) / UNITS_PER_SPE_WORD) \ - : ALTIVEC_REGNO_P (REGNO) \ - ? ((GET_MODE_SIZE (MODE) + UNITS_PER_ALTIVEC_WORD - 1) / UNITS_PER_ALTIVEC_WORD) \ - : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) + to hold something of mode MODE. */ + +#define HARD_REGNO_NREGS(REGNO, MODE) rs6000_hard_regno_nregs ((REGNO), (MODE)) #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \ ((TARGET_32BIT && TARGET_POWERPC64 \ |