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| author | H.J. Lu <hongjiu.lu@intel.com> | 2011-10-25 22:54:48 +0000 |
|---|---|---|
| committer | H.J. Lu <hjl@gcc.gnu.org> | 2011-10-25 15:54:48 -0700 |
| commit | d7115452b2cdceacac0870693d9f44d58e2aab35 (patch) | |
| tree | 42099ce7dee262a414971a4441e23b7466777930 | |
| parent | 95d17cbf6da07f46e0d2a232bb5d102ed53c1855 (diff) | |
| download | gcc-d7115452b2cdceacac0870693d9f44d58e2aab35.zip gcc-d7115452b2cdceacac0870693d9f44d58e2aab35.tar.gz gcc-d7115452b2cdceacac0870693d9f44d58e2aab35.tar.bz2 | |
Remove *mmx_maskmovq_rex.
2011-10-25 H.J. Lu <hongjiu.lu@intel.com>
* config/i386/mmx.md (*mmx_maskmovq): Replace :SI with :P and
remove "&& !TARGET_64BIT"
(*mmx_maskmovq_rex): Removed.
From-SVN: r180458
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/i386/mmx.md | 16 |
2 files changed, 8 insertions, 14 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 06f8ca5..22b9514 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2011-10-25 H.J. Lu <hongjiu.lu@intel.com> + + * config/i386/mmx.md (*mmx_maskmovq): Replace :SI with :P and + remove "&& !TARGET_64BIT" + (*mmx_maskmovq_rex): Removed. + 2011-10-25 Eric Botcazou <ebotcazou@adacore.com> PR rtl-optimization/46603 diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index f092c0f..04c5f9d 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -1656,24 +1656,12 @@ "TARGET_SSE || TARGET_3DNOW_A") (define_insn "*mmx_maskmovq" - [(set (mem:V8QI (match_operand:SI 0 "register_operand" "D")) + [(set (mem:V8QI (match_operand:P 0 "register_operand" "D")) (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y") (match_operand:V8QI 2 "register_operand" "y") (mem:V8QI (match_dup 0))] UNSPEC_MASKMOV))] - "(TARGET_SSE || TARGET_3DNOW_A) && !TARGET_64BIT" - ;; @@@ check ordering of operands in intel/nonintel syntax - "maskmovq\t{%2, %1|%1, %2}" - [(set_attr "type" "mmxcvt") - (set_attr "mode" "DI")]) - -(define_insn "*mmx_maskmovq_rex" - [(set (mem:V8QI (match_operand:DI 0 "register_operand" "D")) - (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y") - (match_operand:V8QI 2 "register_operand" "y") - (mem:V8QI (match_dup 0))] - UNSPEC_MASKMOV))] - "(TARGET_SSE || TARGET_3DNOW_A) && TARGET_64BIT" + "TARGET_SSE || TARGET_3DNOW_A" ;; @@@ check ordering of operands in intel/nonintel syntax "maskmovq\t{%2, %1|%1, %2}" [(set_attr "type" "mmxcvt") |