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| author | Richard Sandiford <richard.sandiford@arm.com> | 2021-04-08 15:00:03 +0100 |
|---|---|---|
| committer | Richard Sandiford <richard.sandiford@arm.com> | 2021-04-08 15:00:03 +0100 |
| commit | d3f78917e1310d7d00e4f955c8e5d30a777f7d35 (patch) | |
| tree | 621e066c4d82180b4d1fd689e7f3f3381780f312 | |
| parent | acbbb82ea3e2ae145e59ffca6f1ec0699b5f7383 (diff) | |
| download | gcc-d3f78917e1310d7d00e4f955c8e5d30a777f7d35.zip gcc-d3f78917e1310d7d00e4f955c8e5d30a777f7d35.tar.gz gcc-d3f78917e1310d7d00e4f955c8e5d30a777f7d35.tar.bz2 | |
testsuite: Fix sve/mul_2.c failures
Some sve/mul_2.c tests were failing because we'd (reasonably)
decided to use shifts and adds instead of MULs for some simple
negative constants. We'd already needed to avoid that when
picking positive constants, so this patch does the same thing
for the negative ones.
gcc/testsuite/
* gcc.target/aarch64/sve/mul_2.c: Adjust negative constants to avoid
conversion to shifts and adds.
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/sve/mul_2.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/mul_2.c b/gcc/testsuite/gcc.target/aarch64/sve/mul_2.c index ff049f5..b57e321 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/mul_2.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/mul_2.c @@ -21,14 +21,14 @@ TEST_TYPE (uint8_t, 32, 2, 250) TEST_TYPE (int8_t, 64, -110, 110) TEST_TYPE (uint8_t, 64, 3, 253) -TEST_TYPE (int16_t, 64, -128, 123) +TEST_TYPE (int16_t, 64, -123, 123) TEST_TYPE (uint16_t, 64, 3, 255) -TEST_TYPE (int8_t, 128, -120, 120) +TEST_TYPE (int8_t, 128, -119, 120) TEST_TYPE (uint8_t, 128, 4, 251) -TEST_TYPE (int16_t, 128, -128, 123) +TEST_TYPE (int16_t, 128, -123, 123) TEST_TYPE (uint16_t, 128, 2, 255) -TEST_TYPE (int32_t, 128, -128, 123) +TEST_TYPE (int32_t, 128, -123, 123) TEST_TYPE (uint32_t, 128, 4, 255) /* { dg-final { scan-assembler-times {\tmul\tz[0-9]+\.b, p[0-7]/m, z[0-9]+\.b, z[0-9]+\.b\n} 6 } } */ @@ -37,9 +37,9 @@ TEST_TYPE (uint32_t, 128, 4, 255) /* { dg-final { scan-assembler-times {\tmul\tz[0-9]+\.b, z[0-9]+\.b, #-100\n} 1 } } */ /* { dg-final { scan-assembler-times {\tmul\tz[0-9]+\.b, z[0-9]+\.b, #-110\n} 1 } } */ -/* { dg-final { scan-assembler-times {\tmul\tz[0-9]+\.b, z[0-9]+\.b, #-120\n} 1 } } */ -/* { dg-final { scan-assembler-times {\tmul\tz[0-9]+\.h, z[0-9]+\.h, #-128\n} 2 } } */ -/* { dg-final { scan-assembler-times {\tmul\tz[0-9]+\.s, z[0-9]+\.s, #-128\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tmul\tz[0-9]+\.b, z[0-9]+\.b, #-119\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tmul\tz[0-9]+\.h, z[0-9]+\.h, #-123\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tmul\tz[0-9]+\.s, z[0-9]+\.s, #-123\n} 1 } } */ /* { dg-final { scan-assembler-times {\tmul\tz[0-9]+\.b, z[0-9]+\.b, #50\n} 6 } } */ /* { dg-final { scan-assembler-times {\tmul\tz[0-9]+\.h, z[0-9]+\.h, #50\n} 4 } } */ |