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| author | Szabolcs Nagy <szabolcs.nagy@arm.com> | 2023-06-02 13:06:21 +0100 |
|---|---|---|
| committer | Szabolcs Nagy <szabolcs.nagy@arm.com> | 2023-11-27 15:52:49 +0000 |
| commit | c9d691a7daa162d6d20927e1e4bf214dad82c5be (patch) | |
| tree | ffb84827cae966e2dd1d90b086965b7932ae3b73 | |
| parent | cad7e1e3e0dea1922f89290bbbc27b4c44f53bf5 (diff) | |
| download | gcc-c9d691a7daa162d6d20927e1e4bf214dad82c5be.zip gcc-c9d691a7daa162d6d20927e1e4bf214dad82c5be.tar.gz gcc-c9d691a7daa162d6d20927e1e4bf214dad82c5be.tar.bz2 | |
aarch64: Disable branch-protection for pcs tests
The tests manipulate the return address in abitest-2.h and thus not
compatible with -mbranch-protection=pac-ret+leaf or
-mbranch-protection=gcs.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/aapcs64/func-ret-1.c: Disable branch-protection.
* gcc.target/aarch64/aapcs64/func-ret-2.c: Likewise.
* gcc.target/aarch64/aapcs64/func-ret-3.c: Likewise.
* gcc.target/aarch64/aapcs64/func-ret-4.c: Likewise.
* gcc.target/aarch64/aapcs64/func-ret-64x1_1.c: Likewise.
5 files changed, 5 insertions, 0 deletions
diff --git a/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-1.c b/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-1.c index 5405e1e..7bd7757 100644 --- a/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-1.c +++ b/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-1.c @@ -4,6 +4,7 @@ AAPCS64 \S 4.1. */ /* { dg-do run { target aarch64*-*-* } } */ +/* { dg-additional-options "-mbranch-protection=none" } */ /* { dg-additional-sources "abitest.S" } */ #ifndef IN_FRAMEWORK diff --git a/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-2.c b/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-2.c index 6b171c4..85a822a 100644 --- a/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-2.c +++ b/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-2.c @@ -4,6 +4,7 @@ Homogeneous floating-point aggregate types are covered in func-ret-3.c. */ /* { dg-do run { target aarch64*-*-* } } */ +/* { dg-additional-options "-mbranch-protection=none" } */ /* { dg-additional-sources "abitest.S" } */ #ifndef IN_FRAMEWORK diff --git a/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-3.c b/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-3.c index ad312b6..1d35ebf 100644 --- a/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-3.c +++ b/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-3.c @@ -4,6 +4,7 @@ in AAPCS64 \S 4.3.5. */ /* { dg-do run { target aarch64-*-* } } */ +/* { dg-additional-options "-mbranch-protection=none" } */ /* { dg-additional-sources "abitest.S" } */ /* { dg-require-effective-target aarch64_big_endian } */ diff --git a/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-4.c b/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-4.c index af05fbe..15e1408 100644 --- a/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-4.c +++ b/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-4.c @@ -5,6 +5,7 @@ are treated as general composite types. */ /* { dg-do run { target aarch64*-*-* } } */ +/* { dg-additional-options "-mbranch-protection=none" } */ /* { dg-additional-sources "abitest.S" } */ /* { dg-require-effective-target aarch64_big_endian } */ diff --git a/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-64x1_1.c b/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-64x1_1.c index 05957e2..fe7bbb6 100644 --- a/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-64x1_1.c +++ b/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-64x1_1.c @@ -3,6 +3,7 @@ Test 64-bit singleton vector types which should be in FP/SIMD registers. */ /* { dg-do run { target aarch64*-*-* } } */ +/* { dg-additional-options "-mbranch-protection=none" } */ /* { dg-additional-sources "abitest.S" } */ #ifndef IN_FRAMEWORK |