(smulsi3_highpart, umulsi3_highpart, mulsidi3, umulsidi3):

Make these conditional on TARGET_MULTM.
(multm matcher): Delete.
(multmu matcher): Delete.
(mulsidi3 DEFINE_SPLIT): Generate RTL for smulsi3_highpart instead of
for deleted pattern.  Fix typo in preparation code.
(umulsidi3 DEFINE_SPLIT): Analogous change.

From-SVN: r8920

1 files changed, 16 insertions, 31 deletions

diff --git a/gcc/config/a29k/a29k.md b/gcc/config/a29k/a29k.md
index 468865c..412f884 100644
--- a/gcc/config/a29k/a29k.md
+++ b/gcc/config/a29k/a29k.md
@@ -1120,32 +1120,12 @@
   ""
   "multiply %0,%1,%2")
 
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(subreg:SI
-	 (mult:DI
-	  (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
-	  (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))) 0))
-   (clobber (match_scratch:SI 3 "=&q"))]
-  ""
-  "multm %0,%1,%2")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(subreg:SI
-	 (mult:DI
-	  (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
-	  (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))) 0))
-   (clobber (match_scratch:SI 3 "=&q"))]
-  ""
-  "multmu %0,%1,%2")
-
 (define_insn "mulsidi3"
   [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
 	(mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
 		 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
    (clobber (match_scratch:SI 3 "=&q"))]
-  ""
+  "TARGET_MULTM"
   "multiply %L0,%1,%2\;multm %0,%1,%2"
   [(set_attr "type" "multi")])
 
@@ -1159,20 +1139,22 @@
 		   (mult:SI (match_dup 1) (match_dup 2)))
 	      (clobber (reg:SI 180))])
    (parallel [(set (match_dup 4)
-		   (subreg:SI (mult:DI
-			       (sign_extend:DI (match_dup 1))
-			       (sign_extend:DI (match_dup 2))) 0))
+		   (truncate:SI
+		    (lshiftrt:DI
+		     (mult:DI (sign_extend:DI (match_dup 1))
+			      (sign_extend:DI (match_dup 2)))
+		     (const_int 32))))
 	      (clobber (reg:SI 180))])]
   "
 { operands[3] = operand_subword (operands[0], 1, 1, DImode);
-  operands[4] = operand_subword (operands[1], 0, 1, DImode); } ")
+  operands[4] = operand_subword (operands[0], 0, 1, DImode); } ")
 			    
 (define_insn "umulsidi3"
   [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
 	(mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
 		 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
    (clobber (match_scratch:SI 3 "=&q"))]
-  ""
+  "TARGET_MULTM"
   "multiplu %L0,%1,%2\;multmu %0,%1,%2"
   [(set_attr "type" "multi")])
 
@@ -1186,12 +1168,15 @@
 		   (mult:SI (match_dup 1) (match_dup 2)))
 	      (clobber (reg:SI 180))])
    (parallel [(set (match_dup 4)
-		   (subreg:SI (mult:DI (zero_extend:DI (match_dup 1))
-				       (zero_extend:DI (match_dup 2))) 0))
+		   (truncate:SI
+		    (lshiftrt:DI
+		     (mult:DI (zero_extend:DI (match_dup 1))
+			      (zero_extend:DI (match_dup 2)))
+		     (const_int 32))))
 	      (clobber (reg:SI 180))])]
   "
 { operands[3] = operand_subword (operands[0], 1, 1, DImode);
-  operands[4] = operand_subword (operands[1], 0, 1, DImode); } ")
+  operands[4] = operand_subword (operands[0], 0, 1, DImode); } ")
 			    
 (define_insn "smulsi3_highpart"
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
@@ -1201,7 +1186,7 @@
 		   (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r")))
 	  (const_int 32))))
    (clobber (match_scratch:SI 3 "=&q"))]
-  ""
+  "TARGET_MULTM"
   "multm %0,%1,%2")
 
 (define_insn "umulsi3_highpart"
@@ -1212,7 +1197,7 @@
 		   (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r")))
 	  (const_int 32))))
    (clobber (match_scratch:SI 3 "=&q"))]
-  ""
+  "TARGET_MULTM"
   "multmu %0,%1,%2")
 
 ;; NAND