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| author | Wilco Dijkstra <wdijkstr@arm.com> | 2016-12-16 12:59:41 +0000 |
|---|---|---|
| committer | Wilco Dijkstra <wilco@gcc.gnu.org> | 2016-12-16 12:59:41 +0000 |
| commit | c67b6f268397b2fc20e72da19e276d2b027ddee4 (patch) | |
| tree | 15b1b309ca187496afcdc2bbad1df74ad52b4171 | |
| parent | bfb688ae91574454758ab0431a9c7a921d53779f (diff) | |
| download | gcc-c67b6f268397b2fc20e72da19e276d2b027ddee4.zip gcc-c67b6f268397b2fc20e72da19e276d2b027ddee4.tar.gz gcc-c67b6f268397b2fc20e72da19e276d2b027ddee4.tar.bz2 | |
Thumb uses a special register allocation order to increase the use of low registers.
Thumb uses a special register allocation order to increase the use of low
registers. Oddly enough, LR appears before R12, which means that LR must
be saved and restored even if R12 is available. Swapping R12 and LR means
this simple example now uses R12 as a temporary (just like ARM):
int f(long long a, long long b)
{
if (a < b) return 1;
return a + b;
}
gcc/
* config/arm/arm.c (thumb_core_reg_alloc_order): Swap R12 and R14.
From-SVN: r243744
| -rw-r--r-- | gcc/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/config/arm/arm.c | 2 |
2 files changed, 5 insertions, 1 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 003f012..daa0458 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,7 @@ +2016-12-16 Wilco Dijkstra <wdijkstr@arm.com> + + * config/arm/arm.c (thumb_core_reg_alloc_order): Swap R12 and R14. + 2016-12-16 Claudiu Zissulescu <claziss@synopsys.com> * config/arc/arc.md (call_prof): Remove. diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 899c001..d0104f9 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -27633,7 +27633,7 @@ arm_mangle_type (const_tree type) static const int thumb_core_reg_alloc_order[] = { 3, 2, 1, 0, 4, 5, 6, 7, - 14, 12, 8, 9, 10, 11 + 12, 14, 8, 9, 10, 11 }; /* Adjust register allocation order when compiling for Thumb. */ |