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author | Doug Evans <dje@gnu.org> | 1997-03-24 21:11:18 +0000 |
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committer | Doug Evans <dje@gnu.org> | 1997-03-24 21:11:18 +0000 |
commit | be20c0ad6eebcaf81d0b701b290a4ed1b80b7f4d (patch) | |
tree | fd7a29c5533eec8a52b86dc678e2724b2e048a67 | |
parent | 4053f6406ef66d991ca8f147596fd71ed3162c50 (diff) | |
download | gcc-be20c0ad6eebcaf81d0b701b290a4ed1b80b7f4d.zip gcc-be20c0ad6eebcaf81d0b701b290a4ed1b80b7f4d.tar.gz gcc-be20c0ad6eebcaf81d0b701b290a4ed1b80b7f4d.tar.bz2 |
Add m32r support.
From-SVN: r13784
-rw-r--r-- | gcc/longlong.h | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/gcc/longlong.h b/gcc/longlong.h index 65a7179..02cc75c 100644 --- a/gcc/longlong.h +++ b/gcc/longlong.h @@ -406,6 +406,33 @@ __w; }) #endif /* __i960__ */ +#if defined (__M32R__) +#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ + /* The cmp clears the condition bit. */ \ + __asm__ ("cmp %0,%0 + addx %%5,%1 + addx %%3,%0" \ + : "=r" ((USItype) (sh)), \ + "=&r" ((USItype) (sl)) \ + : "%0" ((USItype) (ah)), \ + "r" ((USItype) (bh)), \ + "%1" ((USItype) (al)), \ + "r" ((USItype) (bl)) \ + : "cbit") +#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ + /* The cmp clears the condition bit. */ \ + __asm__ ("cmp %0,%0 + subx %5,%1 + subx %3,%0" \ + : "=r" ((USItype) (sh)), \ + "=&r" ((USItype) (sl)) \ + : "0" ((USItype) (ah)), \ + "r" ((USItype) (bh)), \ + "1" ((USItype) (al)), \ + "r" ((USItype) (bl)) \ + : "cbit") +#endif /* __M32R__ */ + #if defined (__mc68000__) #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ __asm__ ("add%.l %5,%1 |