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| author | Andrea Corallo <andrea.corallo@arm.com> | 2022-09-13 19:02:47 +0200 |
|---|---|---|
| committer | Andrea Corallo <andrea.corallo@arm.com> | 2022-11-28 10:06:13 +0100 |
| commit | b9496f8411d1058539d00f716c21397efa43022d (patch) | |
| tree | 3e55529e18d5df6f4188ebf26ff7b814be3e0049 | |
| parent | 9a79b522e0663a202a288db56ebcbdcdb48bdaca (diff) | |
| download | gcc-b9496f8411d1058539d00f716c21397efa43022d.zip gcc-b9496f8411d1058539d00f716c21397efa43022d.tar.gz gcc-b9496f8411d1058539d00f716c21397efa43022d.tar.bz2 | |
arm: fix 'vmsr' spacing and register capitalization
gcc/ChangeLog:
* config/arm/vfp.md (*thumb2_movhi_vfp, *thumb2_movhi_fp16): Fix
'vmsr' spacing and reg capitalization.
gcc/testsuite/ChangeLog:
* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_f32.c:
Update test.
* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_s32.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_u32.c:
Likewise.
4 files changed, 7 insertions, 7 deletions
diff --git a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md index d0f423c..932e4b7 100644 --- a/gcc/config/arm/vfp.md +++ b/gcc/config/arm/vfp.md @@ -105,9 +105,9 @@ case 8: return "vmov%?.f32\t%0, %1\t%@ int"; case 9: - return "vmsr%?\t P0, %1\t@ movhi"; + return "vmsr%?\tp0, %1\t@ movhi"; case 10: - return "vmrs%?\t %0, P0\t@ movhi"; + return "vmrs%?\t%0, p0\t@ movhi"; default: gcc_unreachable (); } @@ -209,9 +209,9 @@ case 8: return "vmov%?.f32\t%0, %1\t%@ int"; case 9: - return "vmsr%?\t P0, %1\t%@ movhi"; + return "vmsr%?\tp0, %1\t%@ movhi"; case 10: - return "vmrs%?\t%0, P0\t%@ movhi"; + return "vmrs%?\t%0, p0\t%@ movhi"; default: gcc_unreachable (); } diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_f32.c index f3219e2..1e57ca4 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_f32.c @@ -11,7 +11,7 @@ foo (uint32x4_t * addr, mve_pred16_t p) } /* { dg-final { scan-assembler "vldrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */ -/* { dg-final { scan-assembler "vmsr\t P0, r\[0-9\]+.*" } } */ +/* { dg-final { scan-assembler "vmsr\tp0, r\[0-9\]+.*" } } */ /* { dg-final { scan-assembler "vpst" } } */ /* { dg-final { scan-assembler "vldrwt.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */ /* { dg-final { scan-assembler "vstrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_s32.c index 4d093d2..f8d77fd 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_s32.c @@ -11,7 +11,7 @@ foo (uint32x4_t * addr, mve_pred16_t p) } /* { dg-final { scan-assembler "vldrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */ -/* { dg-final { scan-assembler "vmsr\t P0, r\[0-9\]+.*" } } */ +/* { dg-final { scan-assembler "vmsr\tp0, r\[0-9\]+.*" } } */ /* { dg-final { scan-assembler "vpst" } } */ /* { dg-final { scan-assembler "vldrwt.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */ /* { dg-final { scan-assembler "vstrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_u32.c index e796522..8a0e109 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_u32.c @@ -11,7 +11,7 @@ foo (uint32x4_t * addr, mve_pred16_t p) } /* { dg-final { scan-assembler "vldrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */ -/* { dg-final { scan-assembler "vmsr\t P0, r\[0-9\]+.*" } } */ +/* { dg-final { scan-assembler "vmsr\tp0, r\[0-9\]+.*" } } */ /* { dg-final { scan-assembler "vpst" } } */ /* { dg-final { scan-assembler "vldrwt.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */ /* { dg-final { scan-assembler "vstrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */ |