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| author | Patrick O'Neill <patrick@rivosinc.com> | 2023-10-30 15:51:46 -0700 |
|---|---|---|
| committer | Patrick O'Neill <patrick@rivosinc.com> | 2023-10-31 10:15:33 -0700 |
| commit | b93fddba394cf19d8a9fd1739314b6c57425be01 (patch) | |
| tree | e3b55f56a73da0366627ca732b324f50705400cc | |
| parent | 60d6c63df00e047ebee74b7bad9b076e55e50f28 (diff) | |
| download | gcc-b93fddba394cf19d8a9fd1739314b6c57425be01.zip gcc-b93fddba394cf19d8a9fd1739314b6c57425be01.tar.gz gcc-b93fddba394cf19d8a9fd1739314b6c57425be01.tar.bz2 | |
RISC-V: Let non-atomic targets use optimized amo loads/stores
Non-atomic targets are currently prevented from using the optimized fencing for
seq_cst load/seq_cst store. This patch removes that constraint.
gcc/ChangeLog:
* config/riscv/sync-rvwmo.md (atomic_load_rvwmo<mode>): Remove
TARGET_ATOMIC constraint
(atomic_store_rvwmo<mode>): Ditto.
* config/riscv/sync-ztso.md (atomic_load_ztso<mode>): Ditto.
(atomic_store_ztso<mode>): Ditto.
* config/riscv/sync.md (atomic_load<mode>): Ditto.
(atomic_store<mode>): Ditto.
Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
| -rw-r--r-- | gcc/config/riscv/sync-rvwmo.md | 4 | ||||
| -rw-r--r-- | gcc/config/riscv/sync-ztso.md | 4 | ||||
| -rw-r--r-- | gcc/config/riscv/sync.md | 4 |
3 files changed, 6 insertions, 6 deletions
diff --git a/gcc/config/riscv/sync-rvwmo.md b/gcc/config/riscv/sync-rvwmo.md index cb641ea..c35eae1 100644 --- a/gcc/config/riscv/sync-rvwmo.md +++ b/gcc/config/riscv/sync-rvwmo.md @@ -52,7 +52,7 @@ [(match_operand:GPR 1 "memory_operand" "A") (match_operand:SI 2 "const_int_operand")] ;; model UNSPEC_ATOMIC_LOAD))] - "TARGET_ATOMIC && !TARGET_ZTSO" + "!TARGET_ZTSO" { enum memmodel model = (enum memmodel) INTVAL (operands[2]); model = memmodel_base (model); @@ -78,7 +78,7 @@ [(match_operand:GPR 1 "reg_or_0_operand" "rJ") (match_operand:SI 2 "const_int_operand")] ;; model UNSPEC_ATOMIC_STORE))] - "TARGET_ATOMIC && !TARGET_ZTSO" + "!TARGET_ZTSO" { enum memmodel model = (enum memmodel) INTVAL (operands[2]); model = memmodel_base (model); diff --git a/gcc/config/riscv/sync-ztso.md b/gcc/config/riscv/sync-ztso.md index 7bb15b7..6fdfa91 100644 --- a/gcc/config/riscv/sync-ztso.md +++ b/gcc/config/riscv/sync-ztso.md @@ -46,7 +46,7 @@ [(match_operand:GPR 1 "memory_operand" "A") (match_operand:SI 2 "const_int_operand")] ;; model UNSPEC_ATOMIC_LOAD))] - "TARGET_ATOMIC && TARGET_ZTSO" + "TARGET_ZTSO" { enum memmodel model = (enum memmodel) INTVAL (operands[2]); model = memmodel_base (model); @@ -66,7 +66,7 @@ [(match_operand:GPR 1 "reg_or_0_operand" "rJ") (match_operand:SI 2 "const_int_operand")] ;; model UNSPEC_ATOMIC_STORE))] - "TARGET_ATOMIC && TARGET_ZTSO" + "TARGET_ZTSO" { enum memmodel model = (enum memmodel) INTVAL (operands[2]); model = memmodel_base (model); diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index 6ff3493..ec9d4b4 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -60,7 +60,7 @@ [(match_operand:GPR 0 "register_operand") (match_operand:GPR 1 "memory_operand") (match_operand:SI 2 "const_int_operand")] ;; model - "TARGET_ATOMIC" + "" { if (TARGET_ZTSO) emit_insn (gen_atomic_load_ztso<mode> (operands[0], operands[1], @@ -75,7 +75,7 @@ [(match_operand:GPR 0 "memory_operand") (match_operand:GPR 1 "reg_or_0_operand") (match_operand:SI 2 "const_int_operand")] ;; model - "TARGET_ATOMIC" + "" { if (TARGET_ZTSO) emit_insn (gen_atomic_store_ztso<mode> (operands[0], operands[1], |