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| author | Maciej W. Rozycki <macro@embecosm.com> | 2023-11-22 01:18:32 +0000 |
|---|---|---|
| committer | Maciej W. Rozycki <macro@embecosm.com> | 2023-11-22 01:18:32 +0000 |
| commit | ae098dfeeefe74968530289d9f5e3ae6f78097bb (patch) | |
| tree | 050b8663c0afa3ea46134167074c100efd310c60 | |
| parent | 6300e672c86236720952227bc4fd6a6dc4eeb55a (diff) | |
| download | gcc-ae098dfeeefe74968530289d9f5e3ae6f78097bb.zip gcc-ae098dfeeefe74968530289d9f5e3ae6f78097bb.tar.gz gcc-ae098dfeeefe74968530289d9f5e3ae6f78097bb.tar.bz2 | |
RISC-V: Remove duplicate `order_operator' predicate
Remove our RISC-V-specific `order_operator' predicate, which is exactly
the same as generic `ordered_comparison_operator' one.
gcc/
* config/riscv/predicates.md (order_operator): Remove predicate.
* config/riscv/riscv.cc (riscv_rtx_costs): Update accordingly.
* config/riscv/riscv.md (*branch<mode>, *mov<GPR:mode><X:mode>cc)
(cstore<mode>4): Likewise.
| -rw-r--r-- | gcc/config/riscv/predicates.md | 3 | ||||
| -rw-r--r-- | gcc/config/riscv/riscv.cc | 2 | ||||
| -rw-r--r-- | gcc/config/riscv/riscv.md | 6 |
3 files changed, 4 insertions, 7 deletions
diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md index 271c07a..ff213e5 100644 --- a/gcc/config/riscv/predicates.md +++ b/gcc/config/riscv/predicates.md @@ -339,9 +339,6 @@ (define_predicate "equality_operator" (match_code "eq,ne")) -(define_predicate "order_operator" - (match_code "eq,ne,lt,ltu,le,leu,ge,geu,gt,gtu")) - (define_predicate "signed_order_operator" (match_code "eq,ne,lt,le,ge,gt")) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 99e64e8..d0efb93 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -2943,7 +2943,7 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN *total = COSTS_N_INSNS (SINGLE_SHIFT_COST + 1); return true; } - if (order_operator (XEXP (x, 0), mode)) + if (ordered_comparison_operator (XEXP (x, 0), mode)) { *total = COSTS_N_INSNS (1); return true; diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 6326def..935eeb7 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -2640,7 +2640,7 @@ (define_insn "*branch<mode>" [(set (pc) (if_then_else - (match_operator 1 "order_operator" + (match_operator 1 "ordered_comparison_operator" [(match_operand:X 2 "register_operand" "r") (match_operand:X 3 "reg_or_0_operand" "rJ")]) (label_ref (match_operand 0 "" "")) @@ -2716,7 +2716,7 @@ (define_insn "*mov<GPR:mode><X:mode>cc" [(set (match_operand:GPR 0 "register_operand" "=r,r") (if_then_else:GPR - (match_operator 5 "order_operator" + (match_operator 5 "ordered_comparison_operator" [(match_operand:X 1 "register_operand" "r,r") (match_operand:X 2 "reg_or_0_operand" "rJ,rJ")]) (match_operand:GPR 3 "register_operand" "0,0") @@ -2902,7 +2902,7 @@ (define_expand "cstore<mode>4" [(set (match_operand:SI 0 "register_operand") - (match_operator:SI 1 "order_operator" + (match_operator:SI 1 "ordered_comparison_operator" [(match_operand:GPR 2 "register_operand") (match_operand:GPR 3 "nonmemory_operand")]))] "" |