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authorJeff Law <jlaw@ventanamicro.com>2023-10-11 16:18:22 -0600
committerJeff Law <jlaw@ventanamicro.com>2023-10-11 16:25:45 -0600
commita3e50ee96dc3e25ca52608e58c4e653f9976cb4e (patch)
treea65969e916e1139e76dcb79632ee8074cbed493a
parentfaae30c49560f1481f036061fa2f894b0f7257f8 (diff)
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RISC-V Adjust long unconditional branch sequence
Andrew and I independently noted the long unconditional branch sequence was using the "call" pseudo op. Technically it works, but it's a bit odd. This patch flips it to use the "jump" pseudo-op. This was tested with a hacked-up local compiler which forced all branches/jumps to be long jumps. Naturally it triggered some failures for scan-asm tests but no execution regressions (which is mostly what I was testing for). I've updated the long branch support item in the RISE wiki to indicate that we eventually want a register scavenging approach with a fallback to $ra in the future so that we don't muck up the return address predictors. It's not super-high priority and shouldn't be terrible to implement given we've got the $ra fallback when a suitable register can not be found. gcc/ * config/riscv/riscv.md (jump): Adjust sequence to use a "jump" pseudo op instead of a "call" pseudo op.
-rw-r--r--gcc/config/riscv/riscv.md2
1 files changed, 1 insertions, 1 deletions
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index c26541b..23d9133 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -2924,7 +2924,7 @@
/* Hopefully this does not happen often as this is going
to clobber $ra and muck up the return stack predictors. */
if (get_attr_length (insn) == 8)
- return "call\t%l0";
+ return "jump\t%l0,ra";
return "j\t%l0";
}