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| author | Kyrylo Tkachov <kyrylo.tkachov@arm.com> | 2023-04-25 14:52:37 +0100 |
|---|---|---|
| committer | Kyrylo Tkachov <kyrylo.tkachov@arm.com> | 2023-04-25 14:54:57 +0100 |
| commit | 9e9503e7b2c1517e8c46ea4d2e8805cc20301f34 (patch) | |
| tree | 6260096d8909e805907aff0b7e918a1861ff25bd | |
| parent | c69db3ef7f7d82a50f46038aa5457b7c8cc2d643 (diff) | |
| download | gcc-9e9503e7b2c1517e8c46ea4d2e8805cc20301f34.zip gcc-9e9503e7b2c1517e8c46ea4d2e8805cc20301f34.tar.gz gcc-9e9503e7b2c1517e8c46ea4d2e8805cc20301f34.tar.bz2 | |
aarch64: PR target/PR99195 Annotate more simple integer binary patterns with vcz subst rules
This patch adds more straightforward annotations to some more integer binary ops to
eliminate redundant fmovs around 64-bit SIMD results.
Bootstrapped and tested on aarch64-none-linux.
gcc/ChangeLog:
PR target/99195
* config/aarch64/aarch64-simd.md (orn<mode>3): Rename to...
(orn<mode>3<vczle><vczbe>): ... This.
(bic<mode>3): Rename to...
(bic<mode>3<vczle><vczbe>): ... This.
(<su><maxmin><mode>3): Rename to...
(<su><maxmin><mode>3<vczle><vczbe>): ... This.
gcc/testsuite/ChangeLog:
PR target/99195
* gcc.target/aarch64/simd/pr99195_1.c: Add tests for orn, bic, max and min.
| -rw-r--r-- | gcc/config/aarch64/aarch64-simd.md | 6 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/simd/pr99195_1.c | 19 |
2 files changed, 12 insertions, 13 deletions
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 5e1b4b1..cb2223d 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -423,7 +423,7 @@ (set_attr "length" "4")] ) -(define_insn "orn<mode>3" +(define_insn "orn<mode>3<vczle><vczbe>" [(set (match_operand:VDQ_I 0 "register_operand" "=w") (ior:VDQ_I (not:VDQ_I (match_operand:VDQ_I 1 "register_operand" "w")) (match_operand:VDQ_I 2 "register_operand" "w")))] @@ -432,7 +432,7 @@ [(set_attr "type" "neon_logic<q>")] ) -(define_insn "bic<mode>3" +(define_insn "bic<mode>3<vczle><vczbe>" [(set (match_operand:VDQ_I 0 "register_operand" "=w") (and:VDQ_I (not:VDQ_I (match_operand:VDQ_I 1 "register_operand" "w")) (match_operand:VDQ_I 2 "register_operand" "w")))] @@ -1671,7 +1671,7 @@ ) ;; Max/Min operations. -(define_insn "<su><maxmin><mode>3" +(define_insn "<su><maxmin><mode>3<vczle><vczbe>" [(set (match_operand:VDQ_BHSI 0 "register_operand" "=w") (MAXMIN:VDQ_BHSI (match_operand:VDQ_BHSI 1 "register_operand" "w") (match_operand:VDQ_BHSI 2 "register_operand" "w")))] diff --git a/gcc/testsuite/gcc.target/aarch64/simd/pr99195_1.c b/gcc/testsuite/gcc.target/aarch64/simd/pr99195_1.c index 3fe0e53..5304e14 100644 --- a/gcc/testsuite/gcc.target/aarch64/simd/pr99195_1.c +++ b/gcc/testsuite/gcc.target/aarch64/simd/pr99195_1.c @@ -37,18 +37,17 @@ OPFOUR (T, IS, OS, S, OP2, OP3, OP4, OP5) FUNC (T, IS, OS, OP1, S) \ OPFIVE (T, IS, OS, S, OP2, OP3, OP4, OP5, OP6) -#define OPSEVEN(T,IS,OS,S,OP1,OP2,OP3,OP4,OP5,OP6,OP7) \ -FUNC (T, IS, OS, OP1, S) \ -OPSIX (T, IS, OS, S, OP2, OP3, OP4, OP5, OP6, OP7) - +#define OPELEVEN(T,IS,OS,S,OP1,OP2,OP3,OP4,OP5,OP6,OP7,OP8,OP9,OP10,OP11) \ +OPFIVE (T, IS, OS, S, OP1, OP2, OP3, OP4, OP5) \ +OPSIX (T, IS, OS, S, OP6, OP7, OP8, OP9, OP10, OP11) -OPSEVEN (int8, 8, 16, s8, padd, add, sub, mul, and, orr, eor) -OPSEVEN (int16, 4, 8, s16, padd, add, sub, mul, and, orr, eor) -OPSEVEN (int32, 2, 4, s32, padd, add, sub, mul, and, orr, eor) +OPELEVEN (int8, 8, 16, s8, padd, add, sub, mul, and, orr, eor, orn, bic, max, min) +OPELEVEN (int16, 4, 8, s16, padd, add, sub, mul, and, orr, eor, orn, bic, max, min) +OPELEVEN (int32, 2, 4, s32, padd, add, sub, mul, and, orr, eor, orn, bic, max, min) -OPSEVEN (uint8, 8, 16, u8, padd, add, sub, mul, and, orr, eor) -OPSEVEN (uint16, 4, 8, u16, padd, add, sub, mul, and, orr, eor) -OPSEVEN (uint32, 2, 4, u32, padd, add, sub, mul, and, orr, eor) +OPELEVEN (uint8, 8, 16, u8, padd, add, sub, mul, and, orr, eor, orn, bic, max, min) +OPELEVEN (uint16, 4, 8, u16, padd, add, sub, mul, and, orr, eor, orn, bic, max, min) +OPELEVEN (uint32, 2, 4, u32, padd, add, sub, mul, and, orr, eor, orn, bic, max, min) /* { dg-final { scan-assembler-not {\tfmov\t} } } */ /* { dg-final { scan-assembler-not {\tmov\t} } } */ |