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| author | Thomas Schwinge <thomas@codesourcery.com> | 2023-11-16 23:17:36 +0100 |
|---|---|---|
| committer | Thomas Schwinge <thomas@codesourcery.com> | 2023-11-30 15:42:57 +0100 |
| commit | 9bd6ee8a82e53ae7e3cb8c83830b3b3e106e2dc0 (patch) | |
| tree | 279ac00a8da15901d41b0600a74b45aede3bd1f3 | |
| parent | 318f5232cfb3e0c9694889565e1f5424d0354463 (diff) | |
| download | gcc-9bd6ee8a82e53ae7e3cb8c83830b3b3e106e2dc0.zip gcc-9bd6ee8a82e53ae7e3cb8c83830b3b3e106e2dc0.tar.gz gcc-9bd6ee8a82e53ae7e3cb8c83830b3b3e106e2dc0.tar.bz2 | |
GCN: Generally enable the 'gcc.target/gcn/avgpr-[...]' test cases
... added in commit ae0d2c240213c5a7f6959c032bfc9f0703cab787
"amdgcn: Add Accelerator VGPR registers". This way, they're correctly tested
no matter what '-march=[...]' is used with 'make check'.
gcc/testsuite/
* gcc.target/gcn/avgpr-mem-double.c: Remove
'dg-skip-if "incompatible ISA" [...]'.
* gcc.target/gcn/avgpr-mem-int.c: Likewise.
* gcc.target/gcn/avgpr-mem-long.c: Likewise.
* gcc.target/gcn/avgpr-mem-short.c: Likewise.
* gcc.target/gcn/avgpr-spill-double.c: Likewise.
* gcc.target/gcn/avgpr-spill-int.c: Likewise.
* gcc.target/gcn/avgpr-spill-long.c: Likewise.
* gcc.target/gcn/avgpr-spill-short.c: Likewise.
| -rw-r--r-- | gcc/testsuite/gcc.target/gcn/avgpr-mem-double.c | 1 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/gcn/avgpr-mem-int.c | 1 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/gcn/avgpr-mem-long.c | 1 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/gcn/avgpr-mem-short.c | 1 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/gcn/avgpr-spill-double.c | 1 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/gcn/avgpr-spill-int.c | 1 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/gcn/avgpr-spill-long.c | 1 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/gcn/avgpr-spill-short.c | 1 |
8 files changed, 0 insertions, 8 deletions
diff --git a/gcc/testsuite/gcc.target/gcn/avgpr-mem-double.c b/gcc/testsuite/gcc.target/gcn/avgpr-mem-double.c index ce089fb..34317a5 100644 --- a/gcc/testsuite/gcc.target/gcn/avgpr-mem-double.c +++ b/gcc/testsuite/gcc.target/gcn/avgpr-mem-double.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ /* { dg-additional-options "-march=gfx90a -O1" } */ -/* { dg-skip-if "incompatible ISA" { *-*-* } { "-march=gfx90[068]" } } */ /* { dg-final { scan-assembler {load[^\n]*a[0-9[]} } } */ /* { dg-final { scan-assembler {store[^\n]*a[0-9[]} } } */ diff --git a/gcc/testsuite/gcc.target/gcn/avgpr-mem-int.c b/gcc/testsuite/gcc.target/gcn/avgpr-mem-int.c index 03d8148..5ea3755 100644 --- a/gcc/testsuite/gcc.target/gcn/avgpr-mem-int.c +++ b/gcc/testsuite/gcc.target/gcn/avgpr-mem-int.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ /* { dg-additional-options "-march=gfx90a -O1" } */ -/* { dg-skip-if "incompatible ISA" { *-*-* } { "-march=gfx90[068]" } } */ /* { dg-final { scan-assembler {load[^\n]*a[0-9[]} } } */ /* { dg-final { scan-assembler {store[^\n]*a[0-9[]} } } */ diff --git a/gcc/testsuite/gcc.target/gcn/avgpr-mem-long.c b/gcc/testsuite/gcc.target/gcn/avgpr-mem-long.c index dcfb483..b52fc98 100644 --- a/gcc/testsuite/gcc.target/gcn/avgpr-mem-long.c +++ b/gcc/testsuite/gcc.target/gcn/avgpr-mem-long.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ /* { dg-additional-options "-march=gfx90a -O1" } */ -/* { dg-skip-if "incompatible ISA" { *-*-* } { "-march=gfx90[068]" } } */ /* { dg-final { scan-assembler {load[^\n]*a[0-9[]} } } */ /* { dg-final { scan-assembler {store[^\n]*a[0-9[]} } } */ diff --git a/gcc/testsuite/gcc.target/gcn/avgpr-mem-short.c b/gcc/testsuite/gcc.target/gcn/avgpr-mem-short.c index 91cc14e..a3e4a8b 100644 --- a/gcc/testsuite/gcc.target/gcn/avgpr-mem-short.c +++ b/gcc/testsuite/gcc.target/gcn/avgpr-mem-short.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ /* { dg-additional-options "-march=gfx90a -O1" } */ -/* { dg-skip-if "incompatible ISA" { *-*-* } { "-march=gfx90[068]" } } */ /* { dg-final { scan-assembler {load[^\n]*a[0-9[]} } } */ /* { dg-final { scan-assembler {store[^\n]*a[0-9[]} } } */ diff --git a/gcc/testsuite/gcc.target/gcn/avgpr-spill-double.c b/gcc/testsuite/gcc.target/gcn/avgpr-spill-double.c index 3e9996d..53853a4 100644 --- a/gcc/testsuite/gcc.target/gcn/avgpr-spill-double.c +++ b/gcc/testsuite/gcc.target/gcn/avgpr-spill-double.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ /* { dg-additional-options "-march=gfx908 -O1" } */ -/* { dg-skip-if "incompatible ISA" { *-*-* } { "-march=gfx90[06]" } } */ /* { dg-final { scan-assembler "accvgpr" } } */ #define TYPE double diff --git a/gcc/testsuite/gcc.target/gcn/avgpr-spill-int.c b/gcc/testsuite/gcc.target/gcn/avgpr-spill-int.c index 0b64c8e..650f158 100644 --- a/gcc/testsuite/gcc.target/gcn/avgpr-spill-int.c +++ b/gcc/testsuite/gcc.target/gcn/avgpr-spill-int.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ /* { dg-additional-options "-march=gfx908 -O1" } */ -/* { dg-skip-if "incompatible ISA" { *-*-* } { "-march=gfx90[06]" } } */ /* { dg-final { scan-assembler "accvgpr" } } */ #ifndef TYPE diff --git a/gcc/testsuite/gcc.target/gcn/avgpr-spill-long.c b/gcc/testsuite/gcc.target/gcn/avgpr-spill-long.c index 516890d..51f887c 100644 --- a/gcc/testsuite/gcc.target/gcn/avgpr-spill-long.c +++ b/gcc/testsuite/gcc.target/gcn/avgpr-spill-long.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ /* { dg-additional-options "-march=gfx908 -O1" } */ -/* { dg-skip-if "incompatible ISA" { *-*-* } { "-march=gfx90[06]" } } */ /* { dg-final { scan-assembler "accvgpr" } } */ #define TYPE long diff --git a/gcc/testsuite/gcc.target/gcn/avgpr-spill-short.c b/gcc/testsuite/gcc.target/gcn/avgpr-spill-short.c index 1e55684..983d201 100644 --- a/gcc/testsuite/gcc.target/gcn/avgpr-spill-short.c +++ b/gcc/testsuite/gcc.target/gcn/avgpr-spill-short.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ /* { dg-additional-options "-march=gfx908 -O1" } */ -/* { dg-skip-if "incompatible ISA" { *-*-* } { "-march=gfx90[06]" } } */ /* { dg-final { scan-assembler "accvgpr" } } */ #define TYPE short |