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| author | Juzhe-Zhong <juzhe.zhong@rivai.ai> | 2023-08-12 10:30:02 +0800 |
|---|---|---|
| committer | Pan Li <pan2.li@intel.com> | 2023-08-12 12:42:28 +0800 |
| commit | 9890f377013cf1e4f5b9fab8a7287a5380dade1f (patch) | |
| tree | e077a1bf194a55b42215dc2fcbf43680fa3aa0f1 | |
| parent | 8be20733b38c200f375cacf698d6b85e76055bcd (diff) | |
| download | gcc-9890f377013cf1e4f5b9fab8a7287a5380dade1f.zip gcc-9890f377013cf1e4f5b9fab8a7287a5380dade1f.tar.gz gcc-9890f377013cf1e4f5b9fab8a7287a5380dade1f.tar.bz2 | |
RISC-V: Add TAREGT_VECTOR check into VLS modes
This patch fixes bug: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110994
This is caused VLS modes incorrect codes int register allocation.
The original case trigger the ICE is fortran code but I can reproduce
with a C code.
gcc/ChangeLog:
PR target/110994
* config/riscv/riscv-opts.h (TARGET_VECTOR_VLS): Add TARGET_VETOR.
gcc/testsuite/ChangeLog:
PR target/110994
* gcc.target/riscv/rvv/autovec/vls/pr110994.c: New test.
| -rw-r--r-- | gcc/config/riscv/riscv-opts.h | 3 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/pr110994.c | 10 |
2 files changed, 12 insertions, 1 deletions
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h index d6d785d..aeea805 100644 --- a/gcc/config/riscv/riscv-opts.h +++ b/gcc/config/riscv/riscv-opts.h @@ -300,6 +300,7 @@ enum riscv_entity /* We only enable VLS modes for VLA vectorization since fixed length VLMAX mode is the highest priority choice and should not conflict with VLS modes. */ -#define TARGET_VECTOR_VLS (riscv_autovec_preference == RVV_SCALABLE) +#define TARGET_VECTOR_VLS \ + (TARGET_VECTOR && riscv_autovec_preference == RVV_SCALABLE) #endif /* ! GCC_RISCV_OPTS_H */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/pr110994.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/pr110994.c new file mode 100644 index 0000000..fcacc78 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/pr110994.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d --param=riscv-autovec-preference=scalable -O2" } */ + +#include "def.h" + +void foo (int8_t *in, int8_t *out) +{ + v4qi v = *(v4qi*)in; + *(v4qi*)out = v; +} |