riscv: thead: Factor out XThead*-specific peepholes

This patch moves the XThead*-specific peephole passes
into thead-peephole.md with the intend to keep vendor-specific
code separated from RISC-V standard code.

This patch does not contain any functional changes.

gcc/ChangeLog:

	* config/riscv/peephole.md: Remove XThead* peephole passes.
	* config/riscv/thead.md: Include thead-peephole.md.
	* config/riscv/thead-peephole.md: New file.

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>

3 files changed, 76 insertions, 56 deletions

diff --git a/gcc/config/riscv/peephole.md b/gcc/config/riscv/peephole.md
index 67e7046..0ef0c04 100644
--- a/gcc/config/riscv/peephole.md
+++ b/gcc/config/riscv/peephole.md
@@ -38,59 +38,3 @@
 {
   operands[5] = GEN_INT (INTVAL (operands[2]) - INTVAL (operands[5]));
 })
-
-;; XTheadMemPair: merge two SI or DI loads
-(define_peephole2
-  [(set (match_operand:GPR 0 "register_operand" "")
-	(match_operand:GPR 1 "memory_operand" ""))
-   (set (match_operand:GPR 2 "register_operand" "")
-	(match_operand:GPR 3 "memory_operand" ""))]
-  "TARGET_XTHEADMEMPAIR
-  && th_mempair_operands_p (operands, true, <GPR:MODE>mode)"
-  [(parallel [(set (match_dup 0) (match_dup 1))
-	          (set (match_dup 2) (match_dup 3))])]
-{
-  th_mempair_order_operands (operands, true, <GPR:MODE>mode);
-})
-
-;; XTheadMemPair: merge two SI or DI stores
-(define_peephole2
-  [(set (match_operand:GPR 0 "memory_operand" "")
-	(match_operand:GPR 1 "register_operand" ""))
-   (set (match_operand:GPR 2 "memory_operand" "")
-	(match_operand:GPR 3 "register_operand" ""))]
-  "TARGET_XTHEADMEMPAIR
-  && th_mempair_operands_p (operands, false, <GPR:MODE>mode)"
-  [(parallel [(set (match_dup 0) (match_dup 1))
-              (set (match_dup 2) (match_dup 3))])]
-{
-  th_mempair_order_operands (operands, false, <GPR:MODE>mode);
-})
-
-;; XTheadMemPair: merge two SI loads with sign-extension
-(define_peephole2
-  [(set (match_operand:DI 0 "register_operand" "")
-	(sign_extend:DI (match_operand:SI 1 "memory_operand" "")))
-   (set (match_operand:DI 2 "register_operand" "")
-	(sign_extend:DI (match_operand:SI 3 "memory_operand" "")))]
-  "TARGET_XTHEADMEMPAIR && TARGET_64BIT
-  && th_mempair_operands_p (operands, true, SImode)"
-  [(parallel [(set (match_dup 0) (sign_extend:DI (match_dup 1)))
-              (set (match_dup 2) (sign_extend:DI (match_dup 3)))])]
-{
-  th_mempair_order_operands (operands, true, SImode);
-})
-
-;; XTheadMemPair: merge two SI loads with zero-extension
-(define_peephole2
-  [(set (match_operand:DI 0 "register_operand" "")
-	(zero_extend:DI (match_operand:SI 1 "memory_operand" "")))
-   (set (match_operand:DI 2 "register_operand" "")
-	(zero_extend:DI (match_operand:SI 3 "memory_operand" "")))]
-  "TARGET_XTHEADMEMPAIR && TARGET_64BIT
-  && th_mempair_operands_p (operands, true, SImode)"
-  [(parallel [(set (match_dup 0) (zero_extend:DI (match_dup 1)))
-              (set (match_dup 2) (zero_extend:DI (match_dup 3)))])]
-{
-  th_mempair_order_operands (operands, true, SImode);
-})
diff --git a/gcc/config/riscv/thead-peephole.md b/gcc/config/riscv/thead-peephole.md
new file mode 100644
index 0000000..5b829b5
--- /dev/null
+++ b/gcc/config/riscv/thead-peephole.md
@@ -0,0 +1,74 @@
+;; Machine description for T-Head vendor extensions
+;; Copyright (C) 2023 Free Software Foundation, Inc.
+
+;; This file is part of GCC.
+
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 3, or (at your option)
+;; any later version.
+
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;; GNU General Public License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3.  If not see
+;; <http://www.gnu.org/licenses/>.
+
+;; XTheadMemPair: merge two SI or DI loads
+(define_peephole2
+  [(set (match_operand:GPR 0 "register_operand" "")
+	(match_operand:GPR 1 "memory_operand" ""))
+   (set (match_operand:GPR 2 "register_operand" "")
+	(match_operand:GPR 3 "memory_operand" ""))]
+  "TARGET_XTHEADMEMPAIR
+  && th_mempair_operands_p (operands, true, <GPR:MODE>mode)"
+  [(parallel [(set (match_dup 0) (match_dup 1))
+	          (set (match_dup 2) (match_dup 3))])]
+{
+  th_mempair_order_operands (operands, true, <GPR:MODE>mode);
+})
+
+;; XTheadMemPair: merge two SI or DI stores
+(define_peephole2
+  [(set (match_operand:GPR 0 "memory_operand" "")
+	(match_operand:GPR 1 "register_operand" ""))
+   (set (match_operand:GPR 2 "memory_operand" "")
+	(match_operand:GPR 3 "register_operand" ""))]
+  "TARGET_XTHEADMEMPAIR
+  && th_mempair_operands_p (operands, false, <GPR:MODE>mode)"
+  [(parallel [(set (match_dup 0) (match_dup 1))
+              (set (match_dup 2) (match_dup 3))])]
+{
+  th_mempair_order_operands (operands, false, <GPR:MODE>mode);
+})
+
+;; XTheadMemPair: merge two SI loads with sign-extension
+(define_peephole2
+  [(set (match_operand:DI 0 "register_operand" "")
+	(sign_extend:DI (match_operand:SI 1 "memory_operand" "")))
+   (set (match_operand:DI 2 "register_operand" "")
+	(sign_extend:DI (match_operand:SI 3 "memory_operand" "")))]
+  "TARGET_XTHEADMEMPAIR && TARGET_64BIT
+  && th_mempair_operands_p (operands, true, SImode)"
+  [(parallel [(set (match_dup 0) (sign_extend:DI (match_dup 1)))
+              (set (match_dup 2) (sign_extend:DI (match_dup 3)))])]
+{
+  th_mempair_order_operands (operands, true, SImode);
+})
+
+;; XTheadMemPair: merge two SI loads with zero-extension
+(define_peephole2
+  [(set (match_operand:DI 0 "register_operand" "")
+	(zero_extend:DI (match_operand:SI 1 "memory_operand" "")))
+   (set (match_operand:DI 2 "register_operand" "")
+	(zero_extend:DI (match_operand:SI 3 "memory_operand" "")))]
+  "TARGET_XTHEADMEMPAIR && TARGET_64BIT
+  && th_mempair_operands_p (operands, true, SImode)"
+  [(parallel [(set (match_dup 0) (zero_extend:DI (match_dup 1)))
+              (set (match_dup 2) (zero_extend:DI (match_dup 3)))])]
+{
+  th_mempair_order_operands (operands, true, SImode);
+})
diff --git a/gcc/config/riscv/thead.md b/gcc/config/riscv/thead.md
index 840a9ff..29f98de 100644
--- a/gcc/config/riscv/thead.md
+++ b/gcc/config/riscv/thead.md
@@ -361,3 +361,5 @@
   [(set_attr "move_type" "load")
    (set_attr "mode" "DI")
    (set_attr "length" "8")])
+
+(include "thead-peephole.md")