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| author | Andrew Carlotti <andrew.carlotti@arm.com> | 2024-04-12 02:09:57 +0100 |
|---|---|---|
| committer | Andrew Carlotti <andrew.carlotti@arm.com> | 2024-04-13 00:40:48 +0100 |
| commit | 967424dcde6bf2d821b581b8f75b5a839e650fed (patch) | |
| tree | ff51c82421a4ef1b87c60c7b7fdb1fa301c613b3 | |
| parent | b18162759a6d464256b0195bc6447f0a1c9dd5dd (diff) | |
| download | gcc-967424dcde6bf2d821b581b8f75b5a839e650fed.zip gcc-967424dcde6bf2d821b581b8f75b5a839e650fed.tar.gz gcc-967424dcde6bf2d821b581b8f75b5a839e650fed.tar.bz2 | |
aarch64: Add rcpc3 dependency on rcpc2 and rcpc
We don't yet have a separate feature flag for FEAT_LRCPC2 (and adding
one will require extending the feature bitmask). Instead, make the
FEAT_LRCPC2 patterns available when either armv8.4-a or +rcpc3 is
specified. We already have a +rcpc flag, so this dependency can be
specified directly.
Also add an explicit dependance on +rcpc to the FEAT_LRCPC2 patterns, so
that they are disabled with armv8.4-a+norcpc.
The cpunative test needed updating because it used an invalid Features
list, since lrcpc3 requires both ilrcpc and lrcpc to be present.
Without this change, host_detect_local_cpu would return the architecture
string 'armv8-a+dotprod+crc+crypto+rcpc3+norcpc'.
gcc/ChangeLog:
* config/aarch64/aarch64-option-extensions.def: Add RCPC to
RCPC3 dependencies.
* config/aarch64/aarch64.h (AARCH64_ISA_RCPC8_4): Add test for
RCPC3 bit
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/cpunative/info_24: Include lrcpc and ilrcpc.
| -rw-r--r-- | gcc/config/aarch64/aarch64-option-extensions.def | 2 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64.h | 3 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/cpunative/info_24 | 4 |
3 files changed, 5 insertions, 4 deletions
diff --git a/gcc/config/aarch64/aarch64-option-extensions.def b/gcc/config/aarch64/aarch64-option-extensions.def index 3155ecc..42ec0ee 100644 --- a/gcc/config/aarch64/aarch64-option-extensions.def +++ b/gcc/config/aarch64/aarch64-option-extensions.def @@ -153,7 +153,7 @@ AARCH64_FMV_FEATURE("fp16fml", FP16FML, (F16FML)) AARCH64_OPT_FMV_EXTENSION("rcpc", RCPC, (), (), (), "lrcpc") -AARCH64_OPT_FMV_EXTENSION("rcpc3", RCPC3, (), (), (), "lrcpc3") +AARCH64_OPT_FMV_EXTENSION("rcpc3", RCPC3, (RCPC), (), (), "lrcpc3") AARCH64_OPT_FMV_EXTENSION("i8mm", I8MM, (SIMD), (), (), "i8mm") diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h index 45e901c..4fa1dfc 100644 --- a/gcc/config/aarch64/aarch64.h +++ b/gcc/config/aarch64/aarch64.h @@ -242,7 +242,8 @@ constexpr auto AARCH64_FL_DEFAULT_ISA_MODE = AARCH64_FL_SM_OFF; #define AARCH64_ISA_SHA3 (aarch64_isa_flags & AARCH64_FL_SHA3) #define AARCH64_ISA_F16FML (aarch64_isa_flags & AARCH64_FL_F16FML) #define AARCH64_ISA_RCPC (aarch64_isa_flags & AARCH64_FL_RCPC) -#define AARCH64_ISA_RCPC8_4 (aarch64_isa_flags & AARCH64_FL_V8_4A) +#define AARCH64_ISA_RCPC8_4 ((AARCH64_ISA_RCPC && AARCH64_ISA_V8_4A) \ + || (aarch64_isa_flags & AARCH64_FL_RCPC3)) #define AARCH64_ISA_RNG (aarch64_isa_flags & AARCH64_FL_RNG) #define AARCH64_ISA_V8_5A (aarch64_isa_flags & AARCH64_FL_V8_5A) #define AARCH64_ISA_TME (aarch64_isa_flags & AARCH64_FL_TME) diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/info_24 b/gcc/testsuite/gcc.target/aarch64/cpunative/info_24 index 8d3c16a..3c64e00 100644 --- a/gcc/testsuite/gcc.target/aarch64/cpunative/info_24 +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/info_24 @@ -1,8 +1,8 @@ processor : 0 BogoMIPS : 100.00 -Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 asimddp lrcpc3 +Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 asimddp lrcpc ilrcpc lrcpc3 CPU implementer : 0xfe CPU architecture: 8 CPU variant : 0x0 CPU part : 0xd08 -CPU revision : 2
\ No newline at end of file +CPU revision : 2 |