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| author | H.J. Lu <hjl.tools@gmail.com> | 2020-06-20 16:02:42 -0700 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2020-06-22 05:18:47 -0700 |
| commit | 9302421e71e85b4d3766a534ed9e1c4ae1e7a6ca (patch) | |
| tree | 864f45ebe8c5c38ee1b6ad2e23f89e10c03cdb19 | |
| parent | d9aed5f1ccffc019ddf980e349caa3d092755cb4 (diff) | |
| download | gcc-9302421e71e85b4d3766a534ed9e1c4ae1e7a6ca.zip gcc-9302421e71e85b4d3766a534ed9e1c4ae1e7a6ca.tar.gz gcc-9302421e71e85b4d3766a534ed9e1c4ae1e7a6ca.tar.bz2 | |
x86: Skip EXT_REX_SSE_REG_P for vzeroupper optimization
Skip EXT_REX_SSE_REG_P for vzeroupper optimization since upper 16 vector
registers don't trigger SSE <-> AVX transition penalty.
gcc/
PR target/95791
* config/i386/i386.c (ix86_dirflag_mode_needed): Skip
EXT_REX_SSE_REG_P.
gcc/testsuite/
PR target/95791
* gcc.target/i386/pr95791.c: New test.
| -rw-r--r-- | gcc/config/i386/i386.c | 4 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/i386/pr95791.c | 10 |
2 files changed, 13 insertions, 1 deletions
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 3b776c0..37aaa49 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -13846,7 +13846,9 @@ ix86_dirflag_mode_needed (rtx_insn *insn) static bool ix86_check_avx_upper_register (const_rtx exp) { - return SSE_REG_P (exp) && GET_MODE_BITSIZE (GET_MODE (exp)) > 128; + return (SSE_REG_P (exp) + && !EXT_REX_SSE_REG_P (exp) + && GET_MODE_BITSIZE (GET_MODE (exp)) > 128); } /* Return needed mode for entity in optimize_mode_switching pass. */ diff --git a/gcc/testsuite/gcc.target/i386/pr95791.c b/gcc/testsuite/gcc.target/i386/pr95791.c new file mode 100644 index 0000000..26a96d4 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr95791.c @@ -0,0 +1,10 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -mavx512f -mvzeroupper" } */ + +void +f(void) +{ + __asm__ __volatile__("" ::: "zmm16"); +} + +/* { dg-final { scan-assembler-not "vzeroupper" } } */ |