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authorVladimir N. Makarov <vmakarov@redhat.com>2023-10-31 10:54:43 -0400
committerVladimir N. Makarov <vmakarov@redhat.com>2023-10-31 11:45:40 -0400
commit9119b008b4195e06012a485ec01a8bb0e43266be (patch)
treed3747dd736261c38d07c8ed39aee66db4af62c6e
parent3e888f94624294d2b9b34ebfee0916768e5d9c3f (diff)
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[RA]: Fixing LRA cycling for multi-reg variable containing a fixed reg
PR111971 test case uses a multi-reg variable containing a fixed reg. LRA rejects such multi-reg because of this when matching the constraint for an asm insn. The rejection results in LRA cycling. The patch fixes this issue. gcc/ChangeLog: PR rtl-optimization/111971 * lra-constraints.cc: (process_alt_operands): Don't check start hard regs for regs originated from register variables. gcc/testsuite/ChangeLog: PR rtl-optimization/111971 * gcc.target/powerpc/pr111971.c: New test.
-rw-r--r--gcc/lra-constraints.cc9
-rw-r--r--gcc/testsuite/gcc.target/powerpc/pr111971.c10
2 files changed, 16 insertions, 3 deletions
diff --git a/gcc/lra-constraints.cc b/gcc/lra-constraints.cc
index d10a2a3..0607c8b 100644
--- a/gcc/lra-constraints.cc
+++ b/gcc/lra-constraints.cc
@@ -2609,12 +2609,15 @@ process_alt_operands (int only_alternative)
winreg = true;
if (REG_P (op))
{
+ tree decl;
if (hard_regno[nop] >= 0
&& in_hard_reg_set_p (this_alternative_set,
mode, hard_regno[nop])
- && !TEST_HARD_REG_BIT
- (this_alternative_exclude_start_hard_regs,
- hard_regno[nop]))
+ && ((REG_ATTRS (op) && (decl = REG_EXPR (op)) != NULL
+ && VAR_P (decl) && DECL_HARD_REGISTER (decl))
+ || !(TEST_HARD_REG_BIT
+ (this_alternative_exclude_start_hard_regs,
+ hard_regno[nop]))))
win = true;
else if (hard_regno[nop] < 0
&& in_class_p (op, this_alternative, NULL))
diff --git a/gcc/testsuite/gcc.target/powerpc/pr111971.c b/gcc/testsuite/gcc.target/powerpc/pr111971.c
new file mode 100644
index 0000000..7f058bd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr111971.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+void
+foo (unsigned long long *a)
+{
+ register long long d asm ("r0") = 0x24;
+ long long n;
+ asm ("mr %0, %1" : "=r"(n) : "r"(d));
+ *a++ = n;
+}