AArch64: Add movi for 0 moves for scalar types [PR109154]

Following the Neoverse N/V and Cortex-A optimization guides SIMD 0 immediates
should be created with a movi of 0.

At the moment we generate an `fmov .., xzr` which is slower and requires a
GP -> FP transfer.

gcc/ChangeLog:

	PR tree-optimization/109154
	* config/aarch64/aarch64.md (*mov<mode>_aarch64, *movsi_aarch64,
	*movdi_aarch64): Add new w -> Z case.
	* config/aarch64/iterators.md (Vbtype): Add QI and HI.

gcc/testsuite/ChangeLog:

	PR tree-optimization/109154
	* gcc.target/aarch64/fneg-abs_2.c: Updated.
	* gcc.target/aarch64/fneg-abs_4.c: Updated.
	* gcc.target/aarch64/dbl_mov_immediate_1.c: Updated.

5 files changed, 7 insertions, 3 deletions

diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 5d1e0f8..4fcd71a 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -1233,6 +1233,7 @@
   "(register_operand (operands[0], <MODE>mode)
     || aarch64_reg_or_zero (operands[1], <MODE>mode))"
   {@ [cons: =0, 1; attrs: type, arch]
+     [w, Z    ; neon_move      , simd  ] movi\t%0.<Vbtype>, #0
      [r, r    ; mov_reg        , *     ] mov\t%w0, %w1
      [r, M    ; mov_imm        , *     ] mov\t%w0, %1
      [w, D<hq>; neon_move      , simd  ] << aarch64_output_scalar_simd_mov_immediate (operands[1], <MODE>mode);
@@ -1290,6 +1291,7 @@
   "(register_operand (operands[0], SImode)
     || aarch64_reg_or_zero (operands[1], SImode))"
   {@ [cons: =0, 1; attrs: type, arch, length]
+     [w  , Z  ; neon_move, simd, 4] movi\t%0.2d, #0
      [r k, r  ; mov_reg  , *   , 4] mov\t%w0, %w1
      [r  , k  ; mov_reg  , *   , 4] ^
      [r  , M  ; mov_imm  , *   , 4] mov\t%w0, %1
@@ -1323,6 +1325,7 @@
   "(register_operand (operands[0], DImode)
     || aarch64_reg_or_zero (operands[1], DImode))"
   {@ [cons: =0, 1; attrs: type, arch, length]
+     [w, Z  ; neon_move, simd, 4] movi\t%0.2d, #0
      [r, r  ; mov_reg  , *   , 4] mov\t%x0, %x1
      [k, r  ; mov_reg  , *   , 4] mov\t%0, %x1
      [r, k  ; mov_reg  , *   , 4] mov\t%x0, %1
diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md
index f9e2210..1593a8f 100644
--- a/gcc/config/aarch64/iterators.md
+++ b/gcc/config/aarch64/iterators.md
@@ -1300,6 +1300,7 @@
 			  (V4SF "16b") (V2DF  "16b")
 			  (DI   "8b")  (DF    "8b")
 			  (SI   "8b")  (SF    "8b")
+			  (QI   "8b")  (HI    "8b")
 			  (V4BF "8b")  (V8BF  "16b")])
 
 ;; Advanced SIMD vector structure to element modes.
diff --git a/gcc/testsuite/gcc.target/aarch64/dbl_mov_immediate_1.c b/gcc/testsuite/gcc.target/aarch64/dbl_mov_immediate_1.c
index fb9088e..4838f74 100644
--- a/gcc/testsuite/gcc.target/aarch64/dbl_mov_immediate_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/dbl_mov_immediate_1.c
@@ -49,7 +49,7 @@ double d4(void)
 /* { dg-final { scan-assembler-times "mov\tx\[0-9\]+, 25838523252736"       1 } } */
 /* { dg-final { scan-assembler-times "movk\tx\[0-9\]+, 0x40fe, lsl 48"      1 } } */
 /* { dg-final { scan-assembler-times "mov\tx\[0-9\]+, -9223372036854775808" 0 } } */
-/* { dg-final { scan-assembler-times {movi\tv[0-9]+.2d, #0} 1 } } */
+/* { dg-final { scan-assembler-times {movi\tv[0-9]+.4s, #?0} 1 } } */
 /* { dg-final { scan-assembler-times {fneg\tv[0-9]+.2d, v[0-9]+.2d} 1 } } */
 /* { dg-final { scan-assembler-times "fmov\td\[0-9\]+, x\[0-9\]+"           1 } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/fneg-abs_2.c b/gcc/testsuite/gcc.target/aarch64/fneg-abs_2.c
index fb14ec3..eed41ea 100644
--- a/gcc/testsuite/gcc.target/aarch64/fneg-abs_2.c
+++ b/gcc/testsuite/gcc.target/aarch64/fneg-abs_2.c
@@ -20,7 +20,7 @@ float32_t f1 (float32_t a)
 
 /*
 ** f2:
-**	fmov	d[0-9]+, xzr
+**	movi	v[0-9]+.4s, #?0
 **	fneg	v[0-9]+.2d, v[0-9]+.2d
 **	orr	v[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b
 **	ret
diff --git a/gcc/testsuite/gcc.target/aarch64/fneg-abs_4.c b/gcc/testsuite/gcc.target/aarch64/fneg-abs_4.c
index 4ea0105..d45c3d1 100644
--- a/gcc/testsuite/gcc.target/aarch64/fneg-abs_4.c
+++ b/gcc/testsuite/gcc.target/aarch64/fneg-abs_4.c
@@ -8,7 +8,7 @@
 
 /*
 ** negabs:
-**	fmov	d[0-9]+, xzr
+**	movi	v31.4s, #?0
 **	fneg	v[0-9]+.2d, v[0-9]+.2d
 **	orr	v[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b
 **	ret