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authorPan Li <pan2.li@intel.com>2024-06-30 16:48:19 +0800
committerPan Li <pan2.li@intel.com>2024-07-01 20:34:09 +0800
commit7a65ab6b5f38d3018ffd456f278a9fd885487a27 (patch)
tree45b681dd83d1fed6c82788de7c4939b96167ff19
parent6d98e88f61f9b2e6864775ce390e9ce0a1359624 (diff)
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RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 4
This patch would like to add test cases for the unsigned scalar .SAT_ADD IMM form 4. Aka: Form 4: #define DEF_SAT_U_ADD_IMM_FMT_4(T) \ T __attribute__((noinline)) \ sat_u_add_imm_##T##_fmt_4 (T x) \ { \ T ret; \ return __builtin_add_overflow (x, 9, &ret) == 0 ? ret : -1; \ } DEF_SAT_U_ADD_IMM_FMT_4(uint64_t) The below test is passed for this patch. * The rv64gcv regression test. gcc/testsuite/ChangeLog: * gcc.target/riscv/sat_arith.h: Add helper test macro. * gcc.target/riscv/sat_u_add_imm-13.c: New test. * gcc.target/riscv/sat_u_add_imm-14.c: New test. * gcc.target/riscv/sat_u_add_imm-15.c: New test. * gcc.target/riscv/sat_u_add_imm-16.c: New test. * gcc.target/riscv/sat_u_add_imm-run-13.c: New test. * gcc.target/riscv/sat_u_add_imm-run-14.c: New test. * gcc.target/riscv/sat_u_add_imm-run-15.c: New test. * gcc.target/riscv/sat_u_add_imm-run-16.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
-rw-r--r--gcc/testsuite/gcc.target/riscv/sat_arith.h11
-rw-r--r--gcc/testsuite/gcc.target/riscv/sat_u_add_imm-13.c19
-rw-r--r--gcc/testsuite/gcc.target/riscv/sat_u_add_imm-14.c21
-rw-r--r--gcc/testsuite/gcc.target/riscv/sat_u_add_imm-15.c18
-rw-r--r--gcc/testsuite/gcc.target/riscv/sat_u_add_imm-16.c17
-rw-r--r--gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-13.c46
-rw-r--r--gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-14.c46
-rw-r--r--gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-15.c46
-rw-r--r--gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-16.c46
9 files changed, 270 insertions, 0 deletions
diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h b/gcc/testsuite/gcc.target/riscv/sat_arith.h
index 83b294d..75442c9 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
@@ -82,6 +82,14 @@ sat_u_add_imm##IMM##_##T##_fmt_3 (T x) \
return __builtin_add_overflow (x, IMM, &ret) ? -1 : ret; \
}
+#define DEF_SAT_U_ADD_IMM_FMT_4(T, IMM) \
+T __attribute__((noinline)) \
+sat_u_add_imm##IMM##_##T##_fmt_4 (T x) \
+{ \
+ T ret; \
+ return __builtin_add_overflow (x, IMM, &ret) == 0 ? ret : -1; \
+}
+
#define RUN_SAT_U_ADD_IMM_FMT_1(T, x, IMM, expect) \
if (sat_u_add_imm##IMM##_##T##_fmt_1(x) != expect) __builtin_abort ()
@@ -91,6 +99,9 @@ sat_u_add_imm##IMM##_##T##_fmt_3 (T x) \
#define RUN_SAT_U_ADD_IMM_FMT_3(T, x, IMM, expect) \
if (sat_u_add_imm##IMM##_##T##_fmt_3(x) != expect) __builtin_abort ()
+#define RUN_SAT_U_ADD_IMM_FMT_4(T, x, IMM, expect) \
+ if (sat_u_add_imm##IMM##_##T##_fmt_4(x) != expect) __builtin_abort ()
+
/******************************************************************************/
/* Saturation Sub (Unsigned and Signed) */
/******************************************************************************/
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-13.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-13.c
new file mode 100644
index 0000000..a3b2679
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-13.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_add_imm9_uint8_t_fmt_4:
+** addi\s+[atx][0-9]+,\s*a0,\s*9
+** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** neg\s+[atx][0-9]+,\s*[atx][0-9]+
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** andi\s+a0,\s*a0,\s*0xff
+** ret
+*/
+DEF_SAT_U_ADD_IMM_FMT_4(uint8_t, 9)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-14.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-14.c
new file mode 100644
index 0000000..968534b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-14.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_add_imm3_uint16_t_fmt_4:
+** addi\s+[atx][0-9]+,\s*a0,\s*3
+** slli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48
+** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** neg\s+[atx][0-9]+,\s*[atx][0-9]+
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** slli\s+a0,\s*a0,\s*48
+** srli\s+a0,\s*a0,\s*48
+** ret
+*/
+DEF_SAT_U_ADD_IMM_FMT_4(uint16_t, 3)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-15.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-15.c
new file mode 100644
index 0000000..3918d21
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-15.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_add_imm7_uint32_t_fmt_4:
+** addiw\s+[atx][0-9]+,\s*a0,\s*7
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** neg\s+[atx][0-9]+,\s*[atx][0-9]+
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** sext.w\s+a0,\s*a0
+** ret
+*/
+DEF_SAT_U_ADD_IMM_FMT_4(uint32_t, 7)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-16.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-16.c
new file mode 100644
index 0000000..307b815
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-16.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_add_imm8_uint64_t_fmt_4:
+** addi\s+[atx][0-9]+,\s*a0,\s*8
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** neg\s+[atx][0-9]+,\s*[atx][0-9]+
+** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** ret
+*/
+DEF_SAT_U_ADD_IMM_FMT_4(uint64_t, 8)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-13.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-13.c
new file mode 100644
index 0000000..872923e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-13.c
@@ -0,0 +1,46 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_FMT_4(uint8_t, 0)
+DEF_SAT_U_ADD_IMM_FMT_4(uint8_t, 1)
+DEF_SAT_U_ADD_IMM_FMT_4(uint8_t, 254)
+DEF_SAT_U_ADD_IMM_FMT_4(uint8_t, 255)
+
+#define T uint8_t
+#define RUN(T, op, imm, expect) RUN_SAT_U_ADD_IMM_FMT_4(T, op, imm, expect)
+
+T d[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 1, },
+ { 1, 1, 2, },
+ { 0, 254, 254, },
+ { 1, 254, 255, },
+ { 2, 254, 255, },
+ { 0, 255, 255, },
+ { 1, 255, 255, },
+ { 2, 255, 255, },
+ { 255, 255, 255, },
+};
+
+int
+main ()
+{
+ RUN (T, d[0][0], 0, d[0][2]);
+
+ RUN (T, d[1][0], 1, d[1][2]);
+ RUN (T, d[2][0], 1, d[2][2]);
+
+ RUN (T, d[3][0], 254, d[3][2]);
+ RUN (T, d[4][0], 254, d[4][2]);
+ RUN (T, d[5][0], 254, d[5][2]);
+
+ RUN (T, d[6][0], 255, d[6][2]);
+ RUN (T, d[7][0], 255, d[7][2]);
+ RUN (T, d[8][0], 255, d[8][2]);
+ RUN (T, d[9][0], 255, d[9][2]);
+
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-14.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-14.c
new file mode 100644
index 0000000..0b75206
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-14.c
@@ -0,0 +1,46 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_FMT_4(uint16_t, 0)
+DEF_SAT_U_ADD_IMM_FMT_4(uint16_t, 1)
+DEF_SAT_U_ADD_IMM_FMT_4(uint16_t, 65534)
+DEF_SAT_U_ADD_IMM_FMT_4(uint16_t, 65535)
+
+#define T uint16_t
+#define RUN(T, op, imm, expect) RUN_SAT_U_ADD_IMM_FMT_4(T, op, imm, expect)
+
+T d[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 1, },
+ { 1, 1, 2, },
+ { 0, 65534, 65534, },
+ { 1, 65534, 65535, },
+ { 2, 65534, 65535, },
+ { 0, 65535, 65535, },
+ { 1, 65535, 65535, },
+ { 2, 65535, 65535, },
+ { 65535, 65535, 65535, },
+};
+
+int
+main ()
+{
+ RUN (T, d[0][0], 0, d[0][2]);
+
+ RUN (T, d[1][0], 1, d[1][2]);
+ RUN (T, d[2][0], 1, d[2][2]);
+
+ RUN (T, d[3][0], 65534, d[3][2]);
+ RUN (T, d[4][0], 65534, d[4][2]);
+ RUN (T, d[5][0], 65534, d[5][2]);
+
+ RUN (T, d[6][0], 65535, d[6][2]);
+ RUN (T, d[7][0], 65535, d[7][2]);
+ RUN (T, d[8][0], 65535, d[8][2]);
+ RUN (T, d[9][0], 65535, d[9][2]);
+
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-15.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-15.c
new file mode 100644
index 0000000..e548d0c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-15.c
@@ -0,0 +1,46 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_FMT_4(uint32_t, 0)
+DEF_SAT_U_ADD_IMM_FMT_4(uint32_t, 1)
+DEF_SAT_U_ADD_IMM_FMT_4(uint32_t, 4294967294)
+DEF_SAT_U_ADD_IMM_FMT_4(uint32_t, 4294967295)
+
+#define T uint32_t
+#define RUN(T, op, imm, expect) RUN_SAT_U_ADD_IMM_FMT_4(T, op, imm, expect)
+
+T d[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 1, },
+ { 1, 1, 2, },
+ { 0, 4294967294, 4294967294, },
+ { 1, 4294967294, 4294967295, },
+ { 2, 4294967294, 4294967295, },
+ { 0, 4294967295, 4294967295, },
+ { 1, 4294967295, 4294967295, },
+ { 2, 4294967295, 4294967295, },
+ { 4294967295, 4294967295, 4294967295, },
+};
+
+int
+main ()
+{
+ RUN (T, d[0][0], 0, d[0][2]);
+
+ RUN (T, d[1][0], 1, d[1][2]);
+ RUN (T, d[2][0], 1, d[2][2]);
+
+ RUN (T, d[3][0], 4294967294, d[3][2]);
+ RUN (T, d[4][0], 4294967294, d[4][2]);
+ RUN (T, d[5][0], 4294967294, d[5][2]);
+
+ RUN (T, d[6][0], 4294967295, d[6][2]);
+ RUN (T, d[7][0], 4294967295, d[7][2]);
+ RUN (T, d[8][0], 4294967295, d[8][2]);
+ RUN (T, d[9][0], 4294967295, d[9][2]);
+
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-16.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-16.c
new file mode 100644
index 0000000..4335d82
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-16.c
@@ -0,0 +1,46 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_FMT_4(uint64_t, 0)
+DEF_SAT_U_ADD_IMM_FMT_4(uint64_t, 1)
+DEF_SAT_U_ADD_IMM_FMT_4(uint64_t, 18446744073709551614u)
+DEF_SAT_U_ADD_IMM_FMT_4(uint64_t, 18446744073709551615u)
+
+#define T uint64_t
+#define RUN(T, op, imm, expect) RUN_SAT_U_ADD_IMM_FMT_4(T, op, imm, expect)
+
+T d[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 1, },
+ { 1, 1, 2, },
+ { 0, 18446744073709551614u, 18446744073709551614u, },
+ { 1, 18446744073709551614u, 18446744073709551615u, },
+ { 2, 18446744073709551614u, 18446744073709551615u, },
+ { 0, 18446744073709551615u, 18446744073709551615u, },
+ { 1, 18446744073709551615u, 18446744073709551615u, },
+ { 2, 18446744073709551615u, 18446744073709551615u, },
+ { 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, },
+};
+
+int
+main ()
+{
+ RUN (T, d[0][0], 0, d[0][2]);
+
+ RUN (T, d[1][0], 1, d[1][2]);
+ RUN (T, d[2][0], 1, d[2][2]);
+
+ RUN (T, d[3][0], 18446744073709551614u, d[3][2]);
+ RUN (T, d[4][0], 18446744073709551614u, d[4][2]);
+ RUN (T, d[5][0], 18446744073709551614u, d[5][2]);
+
+ RUN (T, d[6][0], 18446744073709551615u, d[6][2]);
+ RUN (T, d[7][0], 18446744073709551615u, d[7][2]);
+ RUN (T, d[8][0], 18446744073709551615u, d[8][2]);
+ RUN (T, d[9][0], 18446744073709551615u, d[9][2]);
+
+ return 0;
+}