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| author | Steve Ellcey <sellcey@mips.com> | 2013-07-11 22:25:44 +0000 |
|---|---|---|
| committer | Steve Ellcey <sje@gcc.gnu.org> | 2013-07-11 22:25:44 +0000 |
| commit | 765000222f8aaac772557a80b56dcc5d217a177a (patch) | |
| tree | 9b5fd8f388a92d9dec987efdacc9f5da94cf0073 | |
| parent | 78039734658d68e1acc5d10ad8e14363ac606ba3 (diff) | |
| download | gcc-765000222f8aaac772557a80b56dcc5d217a177a.zip gcc-765000222f8aaac772557a80b56dcc5d217a177a.tar.gz gcc-765000222f8aaac772557a80b56dcc5d217a177a.tar.bz2 | |
mips.c (mips_conditional_register_usage): Do not use t[0-7] registers in MIPS16 mode when optimizing for size.
2013-07-11 Steve Ellcey <sellcey@mips.com>
* config/mips/mips.c (mips_conditional_register_usage): Do not
use t[0-7] registers in MIPS16 mode when optimizing for size.
From-SVN: r200914
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/mips/mips.c | 24 |
2 files changed, 26 insertions, 3 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 613ede4..1d8c05a 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2013-07-11 Steve Ellcey <sellcey@mips.com> + + * config/mips/mips.c (mips_conditional_register_usage): Do not + use t[0-7] registers in MIPS16 mode when optimizing for size. + 2013-07-11 Sriraman Tallam <tmsriram@google.com> * config/i386/i386.c (dispatch_function_versions): Fix array diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index 3c5469b..3c7e439 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -17199,10 +17199,17 @@ mips_conditional_register_usage (void) } if (TARGET_MIPS16) { - /* In MIPS16 mode, we permit the $t temporary registers to be used - for reload. We prohibit the unused $s registers, since they + /* In MIPS16 mode, we prohibit the unused $s registers, since they are call-saved, and saving them via a MIPS16 register would - probably waste more time than just reloading the value. */ + probably waste more time than just reloading the value. + + We permit the $t temporary registers when optimizing for speed + but not when optimizing for space because using them results in + code that is larger (but faster) then not using them. We do + allow $24 (t8) because it is used in CMP and CMPI instructions + and $25 (t9) because it is used as the function call address in + SVR4 PIC code. */ + fixed_regs[18] = call_used_regs[18] = 1; fixed_regs[19] = call_used_regs[19] = 1; fixed_regs[20] = call_used_regs[20] = 1; @@ -17212,6 +17219,17 @@ mips_conditional_register_usage (void) fixed_regs[26] = call_used_regs[26] = 1; fixed_regs[27] = call_used_regs[27] = 1; fixed_regs[30] = call_used_regs[30] = 1; + if (optimize_size) + { + fixed_regs[8] = call_used_regs[8] = 1; + fixed_regs[9] = call_used_regs[9] = 1; + fixed_regs[10] = call_used_regs[10] = 1; + fixed_regs[11] = call_used_regs[11] = 1; + fixed_regs[12] = call_used_regs[12] = 1; + fixed_regs[13] = call_used_regs[13] = 1; + fixed_regs[14] = call_used_regs[14] = 1; + fixed_regs[15] = call_used_regs[15] = 1; + } /* Do not allow HI and LO to be treated as register operands. There are no MTHI or MTLO instructions (or any real need |