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| author | Richard Kenner <kenner@gcc.gnu.org> | 1994-02-01 06:06:13 -0500 |
|---|---|---|
| committer | Richard Kenner <kenner@gcc.gnu.org> | 1994-02-01 06:06:13 -0500 |
| commit | 6db77abd9e7ba6b593adf73c0d7640c774d33cb7 (patch) | |
| tree | 7e41b74371e8c06600b6c6a7a0e629bbe31bdece | |
| parent | bb562bfc33ca838b0b859532e0be9a166054cecc (diff) | |
| download | gcc-6db77abd9e7ba6b593adf73c0d7640c774d33cb7.zip gcc-6db77abd9e7ba6b593adf73c0d7640c774d33cb7.tar.gz gcc-6db77abd9e7ba6b593adf73c0d7640c774d33cb7.tar.bz2 | |
(minsf3, maxdf3, mindf3): Properly insert constant of zero into
patterns.
From-SVN: r6455
| -rw-r--r-- | gcc/config/alpha/alpha.md | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/gcc/config/alpha/alpha.md b/gcc/config/alpha/alpha.md index 94db72f..ec82ae5 100644 --- a/gcc/config/alpha/alpha.md +++ b/gcc/config/alpha/alpha.md @@ -1,5 +1,5 @@ ;;- Machine description for DEC Alpha for GNU C compiler -;; Copyright (C) 1992, 1993 Free Software Foundation, Inc. +;; Copyright (C) 1992, 1993, 1994 Free Software Foundation, Inc. ;; Contributed by Richard Kenner (kenner@nyu.edu) ;; This file is part of GNU CC. @@ -1675,11 +1675,12 @@ (le:DF (match_operand:DF 1 "reg_or_fp0_operand" "") (match_operand:DF 2 "reg_or_fp0_operand" ""))) (set (match_operand:DF 0 "register_operand" "") - (if_then_else:DF (eq (match_dup 3) (const_int 0)) + (if_then_else:DF (eq (match_dup 3) (match_dup 4)) (match_dup 1) (match_dup 2)))] "TARGET_FP" " { operands[3] = gen_reg_rtx (DFmode); + operands[4] = CONST0_RTX (DFmode); }") (define_expand "mindf3" @@ -1687,11 +1688,12 @@ (lt:DF (match_operand:DF 1 "reg_or_fp0_operand" "") (match_operand:DF 2 "reg_or_fp0_operand" ""))) (set (match_operand:DF 0 "register_operand" "") - (if_then_else:DF (ne (match_dup 3) (const_int 0)) + (if_then_else:DF (ne (match_dup 3) (match_dup 4)) (match_dup 1) (match_dup 2)))] "TARGET_FP" " { operands[3] = gen_reg_rtx (DFmode); + operands[4] = CONST0_RTX (DFmode); }") (define_expand "maxsf3" @@ -1712,7 +1714,7 @@ (lt:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "")) (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" "")))) (set (match_operand:SF 0 "register_operand" "") - (if_then_else:SF (ne (match_dup 3) (const_int 0)) + (if_then_else:SF (ne (match_dup 3) (match_dup 4)) (match_dup 1) (match_dup 2)))] "TARGET_FP" " |