RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 3

This patch would like to add test cases for the unsigned scalar
.SAT_ADD IMM form 3.  Aka:

Form 3:
  #define DEF_SAT_U_ADD_IMM_FMT_3(T)                       \
  T __attribute__((noinline))                              \
  sat_u_add_imm_##T##_fmt_3 (T x)                          \
  {                                                        \
    T ret;                                                 \
    return __builtin_add_overflow (x, 8, &ret) ? -1 : ret; \
  }

DEF_SAT_U_ADD_IMM_FMT_3(uint64_t)

The below test is passed for this patch.
* The rv64gcv regression test.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/sat_arith.h: Add helper test macro.
	* gcc.target/riscv/sat_u_add_imm-10.c: New test.
	* gcc.target/riscv/sat_u_add_imm-11.c: New test.
	* gcc.target/riscv/sat_u_add_imm-12.c: New test.
	* gcc.target/riscv/sat_u_add_imm-9.c: New test.
	* gcc.target/riscv/sat_u_add_imm-run-10.c: New test.
	* gcc.target/riscv/sat_u_add_imm-run-11.c: New test.
	* gcc.target/riscv/sat_u_add_imm-run-12.c: New test.
	* gcc.target/riscv/sat_u_add_imm-run-9.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

9 files changed, 270 insertions, 0 deletions

diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h b/gcc/testsuite/gcc.target/riscv/sat_arith.h
index d94f0fd..83b294d 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
@@ -74,12 +74,23 @@ sat_u_add_imm##IMM##_##T##_fmt_2 (T x)      \
   return (T)(x + IMM) < x ? -1 : (x + IMM); \
 }
 
+#define DEF_SAT_U_ADD_IMM_FMT_3(T, IMM)                    \
+T __attribute__((noinline))                                \
+sat_u_add_imm##IMM##_##T##_fmt_3 (T x)                     \
+{                                                          \
+  T ret;                                                   \
+  return __builtin_add_overflow (x, IMM, &ret) ? -1 : ret; \
+}
+
 #define RUN_SAT_U_ADD_IMM_FMT_1(T, x, IMM, expect) \
   if (sat_u_add_imm##IMM##_##T##_fmt_1(x) != expect) __builtin_abort ()
 
 #define RUN_SAT_U_ADD_IMM_FMT_2(T, x, IMM, expect) \
   if (sat_u_add_imm##IMM##_##T##_fmt_2(x) != expect) __builtin_abort ()
 
+#define RUN_SAT_U_ADD_IMM_FMT_3(T, x, IMM, expect) \
+  if (sat_u_add_imm##IMM##_##T##_fmt_3(x) != expect) __builtin_abort ()
+
 /******************************************************************************/
 /* Saturation Sub (Unsigned and Signed)                                       */
 /******************************************************************************/
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-10.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-10.c
new file mode 100644
index 0000000..24cdd26
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-10.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_add_imm3_uint16_t_fmt_3:
+** addi\s+[atx][0-9]+,\s*a0,\s*3
+** slli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48
+** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** neg\s+[atx][0-9]+,\s*[atx][0-9]+
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** slli\s+a0,\s*a0,\s*48
+** srli\s+a0,\s*a0,\s*48
+** ret
+*/
+DEF_SAT_U_ADD_IMM_FMT_3(uint16_t, 3)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-11.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-11.c
new file mode 100644
index 0000000..f30e240
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-11.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_add_imm7_uint32_t_fmt_3:
+** addiw\s+[atx][0-9]+,\s*a0,\s*7
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** neg\s+[atx][0-9]+,\s*[atx][0-9]+
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** sext.w\s+a0,\s*a0
+** ret
+*/
+DEF_SAT_U_ADD_IMM_FMT_3(uint32_t, 7)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-12.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-12.c
new file mode 100644
index 0000000..561c127
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-12.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_add_imm8_uint64_t_fmt_3:
+** addi\s+[atx][0-9]+,\s*a0,\s*8
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** neg\s+[atx][0-9]+,\s*[atx][0-9]+
+** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** ret
+*/
+DEF_SAT_U_ADD_IMM_FMT_3(uint64_t, 8)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-9.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-9.c
new file mode 100644
index 0000000..5fcd6d7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-9.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_add_imm9_uint8_t_fmt_3:
+** addi\s+[atx][0-9]+,\s*a0,\s*9
+** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** neg\s+[atx][0-9]+,\s*[atx][0-9]+
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** andi\s+a0,\s*a0,\s*0xff
+** ret
+*/
+DEF_SAT_U_ADD_IMM_FMT_3(uint8_t, 9)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-10.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-10.c
new file mode 100644
index 0000000..64924a6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-10.c
@@ -0,0 +1,46 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_FMT_3(uint16_t, 0)
+DEF_SAT_U_ADD_IMM_FMT_3(uint16_t, 1)
+DEF_SAT_U_ADD_IMM_FMT_3(uint16_t, 65534)
+DEF_SAT_U_ADD_IMM_FMT_3(uint16_t, 65535)
+
+#define T                       uint16_t
+#define RUN(T, op, imm, expect) RUN_SAT_U_ADD_IMM_FMT_3(T, op, imm, expect)
+
+T d[][3] = {
+  /* arg_0, arg_1, expect */
+  {      0,     0,      0, },
+  {      0,     1,      1, },
+  {      1,     1,      2, },
+  {      0, 65534,  65534, },
+  {      1, 65534,  65535, },
+  {      2, 65534,  65535, },
+  {      0, 65535,  65535, },
+  {      1, 65535,  65535, },
+  {      2, 65535,  65535, },
+  {  65535, 65535,  65535, },
+};
+
+int
+main ()
+{
+  RUN (T, d[0][0],     0, d[0][2]);
+
+  RUN (T, d[1][0],     1, d[1][2]);
+  RUN (T, d[2][0],     1, d[2][2]);
+
+  RUN (T, d[3][0], 65534, d[3][2]);
+  RUN (T, d[4][0], 65534, d[4][2]);
+  RUN (T, d[5][0], 65534, d[5][2]);
+
+  RUN (T, d[6][0], 65535, d[6][2]);
+  RUN (T, d[7][0], 65535, d[7][2]);
+  RUN (T, d[8][0], 65535, d[8][2]);
+  RUN (T, d[9][0], 65535, d[9][2]);
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-11.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-11.c
new file mode 100644
index 0000000..04f3217
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-11.c
@@ -0,0 +1,46 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_FMT_3(uint32_t, 0)
+DEF_SAT_U_ADD_IMM_FMT_3(uint32_t, 1)
+DEF_SAT_U_ADD_IMM_FMT_3(uint32_t, 4294967294)
+DEF_SAT_U_ADD_IMM_FMT_3(uint32_t, 4294967295)
+
+#define T                       uint32_t
+#define RUN(T, op, imm, expect) RUN_SAT_U_ADD_IMM_FMT_3(T, op, imm, expect)
+
+T d[][3] = {
+  /*     arg_0,      arg_1,      expect */
+  {          0,          0,           0, },
+  {          0,          1,           1, },
+  {          1,          1,           2, },
+  {          0, 4294967294,  4294967294, },
+  {          1, 4294967294,  4294967295, },
+  {          2, 4294967294,  4294967295, },
+  {          0, 4294967295,  4294967295, },
+  {          1, 4294967295,  4294967295, },
+  {          2, 4294967295,  4294967295, },
+  { 4294967295, 4294967295,  4294967295, },
+};
+
+int
+main ()
+{
+  RUN (T, d[0][0],          0, d[0][2]);
+
+  RUN (T, d[1][0],          1, d[1][2]);
+  RUN (T, d[2][0],          1, d[2][2]);
+
+  RUN (T, d[3][0], 4294967294, d[3][2]);
+  RUN (T, d[4][0], 4294967294, d[4][2]);
+  RUN (T, d[5][0], 4294967294, d[5][2]);
+
+  RUN (T, d[6][0], 4294967295, d[6][2]);
+  RUN (T, d[7][0], 4294967295, d[7][2]);
+  RUN (T, d[8][0], 4294967295, d[8][2]);
+  RUN (T, d[9][0], 4294967295, d[9][2]);
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-12.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-12.c
new file mode 100644
index 0000000..8ef6c14
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-12.c
@@ -0,0 +1,46 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_FMT_3(uint64_t, 0)
+DEF_SAT_U_ADD_IMM_FMT_3(uint64_t, 1)
+DEF_SAT_U_ADD_IMM_FMT_3(uint64_t, 18446744073709551614u)
+DEF_SAT_U_ADD_IMM_FMT_3(uint64_t, 18446744073709551615u)
+
+#define T                       uint64_t
+#define RUN(T, op, imm, expect) RUN_SAT_U_ADD_IMM_FMT_3(T, op, imm, expect)
+
+T d[][3] = {
+  /*                arg_0,                 arg_1,                 expect */
+  {                     0,                     0,                      0, },
+  {                     0,                     1,                      1, },
+  {                     1,                     1,                      2, },
+  {                     0, 18446744073709551614u,  18446744073709551614u, },
+  {                     1, 18446744073709551614u,  18446744073709551615u, },
+  {                     2, 18446744073709551614u,  18446744073709551615u, },
+  {                     0, 18446744073709551615u,  18446744073709551615u, },
+  {                     1, 18446744073709551615u,  18446744073709551615u, },
+  {                     2, 18446744073709551615u,  18446744073709551615u, },
+  { 18446744073709551615u, 18446744073709551615u,  18446744073709551615u, },
+};
+
+int
+main ()
+{
+  RUN (T, d[0][0],                     0, d[0][2]);
+
+  RUN (T, d[1][0],                     1, d[1][2]);
+  RUN (T, d[2][0],                     1, d[2][2]);
+
+  RUN (T, d[3][0], 18446744073709551614u, d[3][2]);
+  RUN (T, d[4][0], 18446744073709551614u, d[4][2]);
+  RUN (T, d[5][0], 18446744073709551614u, d[5][2]);
+
+  RUN (T, d[6][0], 18446744073709551615u, d[6][2]);
+  RUN (T, d[7][0], 18446744073709551615u, d[7][2]);
+  RUN (T, d[8][0], 18446744073709551615u, d[8][2]);
+  RUN (T, d[9][0], 18446744073709551615u, d[9][2]);
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-9.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-9.c
new file mode 100644
index 0000000..8867361
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-9.c
@@ -0,0 +1,46 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_FMT_3(uint8_t, 0)
+DEF_SAT_U_ADD_IMM_FMT_3(uint8_t, 1)
+DEF_SAT_U_ADD_IMM_FMT_3(uint8_t, 254)
+DEF_SAT_U_ADD_IMM_FMT_3(uint8_t, 255)
+
+#define T                       uint8_t
+#define RUN(T, op, imm, expect) RUN_SAT_U_ADD_IMM_FMT_3(T, op, imm, expect)
+
+T d[][3] = {
+  /* arg_0, arg_1, expect */
+  {      0,     0,      0, },
+  {      0,     1,      1, },
+  {      1,     1,      2, },
+  {      0,   254,    254, },
+  {      1,   254,    255, },
+  {      2,   254,    255, },
+  {      0,   255,    255, },
+  {      1,   255,    255, },
+  {      2,   255,    255, },
+  {    255,   255,    255, },
+};
+
+int
+main ()
+{
+  RUN (T, d[0][0],   0, d[0][2]);
+
+  RUN (T, d[1][0],   1, d[1][2]);
+  RUN (T, d[2][0],   1, d[2][2]);
+
+  RUN (T, d[3][0], 254, d[3][2]);
+  RUN (T, d[4][0], 254, d[4][2]);
+  RUN (T, d[5][0], 254, d[5][2]);
+
+  RUN (T, d[6][0], 255, d[6][2]);
+  RUN (T, d[7][0], 255, d[7][2]);
+  RUN (T, d[8][0], 255, d[8][2]);
+  RUN (T, d[9][0], 255, d[9][2]);
+
+  return 0;
+}