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| author | Thomas Schwinge <tschwinge@baylibre.com> | 2024-01-31 10:19:00 +0100 |
|---|---|---|
| committer | Thomas Schwinge <tschwinge@baylibre.com> | 2024-02-01 12:27:08 +0100 |
| commit | 6c2a40f4f4577f5d0f7bd1cfda48a5701b75744c (patch) | |
| tree | 524dfb110930013137e4a695ded62fc7143b273c | |
| parent | 75f49cf82e06971b066b4f440256004775603752 (diff) | |
| download | gcc-6c2a40f4f4577f5d0f7bd1cfda48a5701b75744c.zip gcc-6c2a40f4f4577f5d0f7bd1cfda48a5701b75744c.tar.gz gcc-6c2a40f4f4577f5d0f7bd1cfda48a5701b75744c.tar.bz2 | |
GCN, RDNA 3: Adjust 'sync_compare_and_swap<mode>_lds_insn'
For OpenACC/GCN '-march=gfx1100', a lot of libgomp OpenACC test cases FAIL:
/tmp/ccGfLJ8a.mkoffload.2.s:406:2: error: instruction not supported on this GPU
ds_cmpst_rtn_b32 v0, v0, v4, v3
^
In RDNA 3, 'ds_cmpst_[...]' has been replaced by 'ds_cmpstore_[...]', and the
notes for 'ds_cmpst_[...]' in pre-RDNA 3 ISA manuals:
Caution, the order of src and cmp are the *opposite* of the BUFFER_ATOMIC_CMPSWAP opcode.
..., have been resolved for 'ds_cmpstore_[...]' in the RDNA 3 ISA manual:
In this architecture the order of src and cmp agree with the BUFFER_ATOMIC_CMPSWAP opcode.
..., and therefore '%2', '%3' now swapped with regards to GCC operand order.
Most of the affected libgomp OpenACC test cases then PASS their execution test.
gcc/
* config/gcn/gcn.md (sync_compare_and_swap<mode>_lds_insn)
[TARGET_RDNA3]: Adjust.
| -rw-r--r-- | gcc/config/gcn/gcn.md | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/gcc/config/gcn/gcn.md b/gcc/config/gcn/gcn.md index 1f3c692..925e2ce 100644 --- a/gcc/config/gcn/gcn.md +++ b/gcc/config/gcn/gcn.md @@ -2074,7 +2074,12 @@ (match_operand:SIDI 3 "register_operand" " v")] UNSPECV_ATOMIC))] "" - "ds_cmpst_rtn_b<bitsize> %0, %1, %2, %3\;s_waitcnt\tlgkmcnt(0)" + { + if (TARGET_RDNA3) + return "ds_cmpstore_rtn_b<bitsize> %0, %1, %3, %2\;s_waitcnt\tlgkmcnt(0)"; + else + return "ds_cmpst_rtn_b<bitsize> %0, %1, %2, %3\;s_waitcnt\tlgkmcnt(0)"; + } [(set_attr "type" "ds") (set_attr "length" "12")]) |