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| author | Alexander Ivchenko <alexander.ivchenko@intel.com> | 2013-10-11 13:38:15 +0000 |
|---|---|---|
| committer | Kirill Yukhin <kyukhin@gcc.gnu.org> | 2013-10-11 13:38:15 +0000 |
| commit | 67f783cbc3d03913a53ab9dd8c46d82aafe3a671 (patch) | |
| tree | ed84879bd8861aee471d33fc78d6753ac9a477b0 | |
| parent | ec5e777c3e15c4de3f0fbe329dceebd730f7b231 (diff) | |
| download | gcc-67f783cbc3d03913a53ab9dd8c46d82aafe3a671.zip gcc-67f783cbc3d03913a53ab9dd8c46d82aafe3a671.tar.gz gcc-67f783cbc3d03913a53ab9dd8c46d82aafe3a671.tar.bz2 | |
i386.md (multdiv): New.
* config/i386/i386.md (multdiv): New.
(multdiv_mnemonic): Ditto.
* config/i386/sse.md (<sse>_vmmul<mode>3): Changed to...
(<sse>_vm<multdiv_mnemonic><mode>3): This.
(<sse>_vmdiv<mode>3): Removed.
Co-Authored-By: Andrey Turetskiy <andrey.turetskiy@intel.com>
Co-Authored-By: Anna Tikhonova <anna.tikhonova@intel.com>
Co-Authored-By: Ilya Tocar <ilya.tocar@intel.com>
Co-Authored-By: Ilya Verbin <ilya.verbin@intel.com>
Co-Authored-By: Kirill Yukhin <kirill.yukhin@intel.com>
Co-Authored-By: Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Co-Authored-By: Michael Zolotukhin <michael.v.zolotukhin@intel.com>
Co-Authored-By: Sergey Lega <sergey.s.lega@intel.com>
From-SVN: r203432
| -rw-r--r-- | gcc/ChangeLog | 16 | ||||
| -rw-r--r-- | gcc/config/i386/i386.md | 4 | ||||
| -rw-r--r-- | gcc/config/i386/sse.md | 31 |
3 files changed, 27 insertions, 24 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 45cd4ef..c57fa68 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -8,6 +8,22 @@ Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> + * config/i386/i386.md (multdiv): New. + (multdiv_mnemonic): Ditto. + * config/i386/sse.md (<sse>_vmmul<mode>3): Changed to... + (<sse>_vm<multdiv_mnemonic><mode>3): This. + (<sse>_vmdiv<mode>3): Removed. + +2013-10-11 Alexander Ivchenko <alexander.ivchenko@intel.com> + Maxim Kuznetsov <maxim.kuznetsov@intel.com> + Sergey Lega <sergey.s.lega@intel.com> + Anna Tikhonova <anna.tikhonova@intel.com> + Ilya Tocar <ilya.tocar@intel.com> + Andrey Turetskiy <andrey.turetskiy@intel.com> + Ilya Verbin <ilya.verbin@intel.com> + Kirill Yukhin <kirill.yukhin@intel.com> + Michael Zolotukhin <michael.v.zolotukhin@intel.com> + * config/i386/sse.md (V): Extended with wider modes. (VF2): Ditto. (ssehalfvecmode): Ditto. diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 511af95..ad79589 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -746,6 +746,8 @@ (define_code_iterator sat_plusminus [ss_plus us_plus ss_minus us_minus]) +(define_code_iterator multdiv [mult div]) + ;; Base name for define_insn (define_code_attr plusminus_insn [(plus "add") (ss_plus "ssadd") (us_plus "usadd") @@ -757,6 +759,8 @@ (minus "sub") (ss_minus "subs") (us_minus "subus")]) (define_code_attr plusminus_carry_mnemonic [(plus "adc") (minus "sbb")]) +(define_code_attr multdiv_mnemonic + [(mult "mul") (div "div")]) ;; Mark commutative operators as such in constraints. (define_code_attr comm [(plus "%") (ss_plus "%") (us_plus "%") diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index cdb9ae0..89c31c5 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -1061,21 +1061,22 @@ (set_attr "btver2_decode" "direct,double") (set_attr "mode" "<MODE>")]) -(define_insn "<sse>_vmmul<mode>3" +(define_insn "<sse>_vm<multdiv_mnemonic><mode>3" [(set (match_operand:VF_128 0 "register_operand" "=x,v") (vec_merge:VF_128 - (mult:VF_128 + (multdiv:VF_128 (match_operand:VF_128 1 "register_operand" "0,v") (match_operand:VF_128 2 "nonimmediate_operand" "xm,vm")) (match_dup 1) (const_int 1)))] "TARGET_SSE" "@ - mul<ssescalarmodesuffix>\t{%2, %0|%0, %<iptr>2} - vmul<ssescalarmodesuffix>\t{%2, %1, %0|%0, %1, %<iptr>2}" + <multdiv_mnemonic><ssescalarmodesuffix>\t{%2, %0|%0, %<iptr>2} + v<multdiv_mnemonic><ssescalarmodesuffix>\t{%2, %1, %0|%0, %1, %<iptr>2}" [(set_attr "isa" "noavx,avx") - (set_attr "type" "ssemul") - (set_attr "prefix" "orig,vex") + (set_attr "type" "sse<multdiv_mnemonic>") + (set_attr "prefix" "orig,maybe_evex") + (set_attr "btver2_decode" "direct,double") (set_attr "mode" "<ssescalarmode>")]) (define_expand "div<mode>3" @@ -1118,24 +1119,6 @@ (set_attr "prefix" "orig,vex") (set_attr "mode" "<MODE>")]) -(define_insn "<sse>_vmdiv<mode>3" - [(set (match_operand:VF_128 0 "register_operand" "=x,v") - (vec_merge:VF_128 - (div:VF_128 - (match_operand:VF_128 1 "register_operand" "0,v") - (match_operand:VF_128 2 "nonimmediate_operand" "xm,vm")) - (match_dup 1) - (const_int 1)))] - "TARGET_SSE" - "@ - div<ssescalarmodesuffix>\t{%2, %0|%0, %<iptr>2} - vdiv<ssescalarmodesuffix>\t{%2, %1, %0|%0, %1, %<iptr>2}" - [(set_attr "isa" "noavx,avx") - (set_attr "type" "ssediv") - (set_attr "prefix" "orig,vex") - (set_attr "btver2_decode" "direct,double") - (set_attr "mode" "<ssescalarmode>")]) - (define_insn "<sse>_rcp<mode>2" [(set (match_operand:VF1_128_256 0 "register_operand" "=x") (unspec:VF1_128_256 |