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| author | Edwin Lu <ewlu@rivosinc.com> | 2024-06-11 13:50:02 -0700 |
|---|---|---|
| committer | Edwin Lu <ewlu@rivosinc.com> | 2024-06-18 15:28:17 -0700 |
| commit | 6638ba17eadc0f450faa3d8c2f77afe7fdb20614 (patch) | |
| tree | 0b208106540abbdc6a64775d2d2a6bee12dbf3d2 | |
| parent | cbf7245c8b305fe997a535051a4fec379a429243 (diff) | |
| download | gcc-6638ba17eadc0f450faa3d8c2f77afe7fdb20614.zip gcc-6638ba17eadc0f450faa3d8c2f77afe7fdb20614.tar.gz gcc-6638ba17eadc0f450faa3d8c2f77afe7fdb20614.tar.bz2 | |
RISC-V: Fix vwsll combine on rv32 targets
On rv32 targets, vwsll_zext1_scalar_<mode> would trigger an ice in
maybe_legitimize_instruction when zero extending a uint32 to uint64 due
to a mismatch between the input operand's mode (DI) and the expanded insn
operand's mode (Pmode == SI). Ensure that mode of the operands match
gcc/ChangeLog:
* config/riscv/autovec-opt.md: Fix mode mismatch
Signed-off-by: Edwin Lu <ewlu@rivosinc.com>
Co-authored-by: Robin Dapp <rdapp@ventanamicro.com>
| -rw-r--r-- | gcc/config/riscv/autovec-opt.md | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md index 6a2eabb..d7a3cfd 100644 --- a/gcc/config/riscv/autovec-opt.md +++ b/gcc/config/riscv/autovec-opt.md @@ -1517,8 +1517,7 @@ "&& 1" [(const_int 0)] { - if (GET_CODE (operands[2]) == SUBREG) - operands[2] = SUBREG_REG (operands[2]); + operands[2] = gen_lowpart (Pmode, operands[2]); insn_code icode = code_for_pred_vwsll_scalar (<MODE>mode); riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP, operands); DONE; @@ -1584,8 +1583,7 @@ "&& 1" [(const_int 0)] { - if (GET_CODE (operands[2]) == SUBREG) - operands[2] = SUBREG_REG (operands[2]); + operands[2] = gen_lowpart (Pmode, operands[2]); insn_code icode = code_for_pred_vwsll_scalar (<V_DOUBLE_TRUNC>mode); riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP, operands); DONE; |