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| author | Andrey Belevantsev <abel@ispras.ru> | 2016-03-15 18:42:07 +0300 |
|---|---|---|
| committer | Andrey Belevantsev <abel@gcc.gnu.org> | 2016-03-15 18:42:07 +0300 |
| commit | 6598bb55e90fe000eee237d3e7eb7b70c6d5d205 (patch) | |
| tree | 05575a387e521d2f8c625c43922daf99d64faba2 | |
| parent | 11a6609c191c4feae4b744944fa178b1e763c904 (diff) | |
| download | gcc-6598bb55e90fe000eee237d3e7eb7b70c6d5d205.zip gcc-6598bb55e90fe000eee237d3e7eb7b70c6d5d205.tar.gz gcc-6598bb55e90fe000eee237d3e7eb7b70c6d5d205.tar.bz2 | |
re PR rtl-optimization/69032 (ICE: in cfg_preds_1, at sel-sched-ir.c:4809 with -fsched-pressure -fsel-sched-pipelining -fselective-scheduling)
gcc/
PR rtl-optimization/69032
* sel-sched-ir.c (get_seqno_by_preds): Include both insn and head when
looping backwards over basic block insns.
testsuite/
PR rtl-optimization/69032
* gcc.dg/pr69032.c: New test.
From-SVN: r234219
| -rw-r--r-- | gcc/ChangeLog | 12 | ||||
| -rw-r--r-- | gcc/sel-sched-ir.c | 9 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.dg/pr69032.c | 11 |
4 files changed, 34 insertions, 3 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index ac70e8a..de099d6 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,17 @@ 2016-03-15 Andrey Belevantsev <abel@ispras.ru> + PR rtl-optimization/69032 + * sel-sched-ir.c (get_seqno_by_preds): Include both insn and head when + looping backwards over basic block insns. + +2016-03-15 Andrey Belevantsev <abel@ispras.ru> + + PR target/66660 + * sel-sched-ir.c (merge_expr): Avoid changing the speculative pattern + to non-speculative when propagating trap bits. + +2016-03-15 Andrey Belevantsev <abel@ispras.ru> + PR rtl-optimization/63384 * sel-sched.c (invoke_aftermath_hooks): Do not decrease issue_more on DEBUG_INSN_P insns. diff --git a/gcc/sel-sched-ir.c b/gcc/sel-sched-ir.c index 9507853..83f813a 100644 --- a/gcc/sel-sched-ir.c +++ b/gcc/sel-sched-ir.c @@ -4106,11 +4106,14 @@ get_seqno_by_preds (rtx_insn *insn) insn_t *preds; int n, i, seqno; - while (tmp != head) + /* Loop backwards from INSN to HEAD including both. */ + while (1) { - tmp = PREV_INSN (tmp); if (INSN_P (tmp)) - return INSN_SEQNO (tmp); + return INSN_SEQNO (tmp); + if (tmp == head) + break; + tmp = PREV_INSN (tmp); } cfg_preds (bb, &preds, &n); diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 9259910..44f5733 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,10 @@ 2016-03-15 Andrey Belevantsev <abel@ispras.ru> + PR rtl-optimization/69032 + * gcc.dg/pr69032.c: New test. + +2016-03-15 Andrey Belevantsev <abel@ispras.ru> + PR rtl-optimization/63384 * g++.dg/pr63384.C: New test. diff --git a/gcc/testsuite/gcc.dg/pr69032.c b/gcc/testsuite/gcc.dg/pr69032.c new file mode 100644 index 0000000..e0925cd --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr69032.c @@ -0,0 +1,11 @@ +/* { dg-do compile { target powerpc*-*-* ia64-*-* i?86-*-* x86_64-*-* } } */ +/* { dg-options "-O2 -fsched-pressure -fsel-sched-pipelining -fselective-scheduling" } */ + +void foo (long long i) +{ + while (i != -1) + { + ++i; + __asm__ (""); + } +} |