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| author | Juzhe-Zhong <juzhe.zhong@rivai.ai> | 2023-08-23 10:21:22 +0800 |
|---|---|---|
| committer | Pan Li <pan2.li@intel.com> | 2023-08-23 10:22:39 +0800 |
| commit | 5f3c8075f230309c4417b0e5256283d010ac99d2 (patch) | |
| tree | 97c9023483ae8ce41002412023d4059f83423f28 | |
| parent | ea1eb12a38f09e494d5ef072e55653a6463d57eb (diff) | |
| download | gcc-5f3c8075f230309c4417b0e5256283d010ac99d2.zip gcc-5f3c8075f230309c4417b0e5256283d010ac99d2.tar.gz gcc-5f3c8075f230309c4417b0e5256283d010ac99d2.tar.bz2 | |
RISC-V: Fix gather_load_run-12.c test
FAIL: gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-12.c
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-12.c:
Add vsetvli asm.
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-12.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-12.c index b4e2ead..2fb525d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-12.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-12.c @@ -7,6 +7,12 @@ int main (void) { + /* FIXME: The purpose of this assembly is to ensure that the vtype register is + initialized befor instructions such as vmv1r.v are executed. Otherwise you + will get illegal instruction errors when running with spike+pk. This is an + interim solution for reduce unnecessary failures and a unified solution + will come later. */ + asm volatile("vsetivli x0, 0, e8, m1, ta, ma"); #define RUN_LOOP(DATA_TYPE, INDEX_TYPE) \ DATA_TYPE dest_##DATA_TYPE##_##INDEX_TYPE[202] = {0}; \ DATA_TYPE src_##DATA_TYPE##_##INDEX_TYPE[202] = {0}; \ |