aarch64: Merge sqdmlal2 and sqdmlsl2 expanders

The various sqdmlal2 and sqdmlsl2 expanders perform almost identical functions and can be
merged using code iterators and attributes to reduce the code in the MD file.
No behavioural change is expected.

gcc/ChangeLog:

	* config/aarch64/aarch64-simd.md (aarch64_sqdmlal2<mode>): Merge into...
	(aarch64_sqdml<SBINQOPS:as>l2<mode>): ... This.
	(aarch64_sqdmlsl2<mode>): Delete.
	(aarch64_sqdmlal2_lane<mode>): Merge this...
	(aarch64_sqdmlsl2_lane<mode>): ... And this...
	(aarch64_sqdml<SBINQOPS:as>l2_lane<mode>): ... Into this.
	(aarch64_sqdmlal2_laneq<mode>): Merge this...
	(aarch64_sqdmlsl2_laneq<mode>): ... And this...
	(aarch64_sqdml<SBINQOPS:as>l2_laneq<mode>): ... Into this.
	(aarch64_sqdmlal2_n<mode>): Merge this...
	(aarch64_sqdmlsl2_n<mode>): ... And this...
	(aarch64_sqdml<SBINQOPS:as>l2_n<mode>): ... Into this.

1 files changed, 28 insertions, 76 deletions

diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index 9962089..802cca3 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -5356,29 +5356,19 @@
   [(set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")]
 )
 
-(define_expand "aarch64_sqdmlal2<mode>"
+(define_expand "aarch64_sqdml<SBINQOPS:as>l2<mode>"
   [(match_operand:<VWIDE> 0 "register_operand")
-   (match_operand:<VWIDE> 1 "register_operand")
+   (SBINQOPS:<VWIDE>
+     (match_operand:<VWIDE> 1 "register_operand")
+     (match_dup 1))
    (match_operand:VQ_HSI 2 "register_operand")
    (match_operand:VQ_HSI 3 "register_operand")]
   "TARGET_SIMD"
 {
   rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true);
-  emit_insn (gen_aarch64_sqdmlal2<mode>_internal (operands[0], operands[1],
-						  operands[2], operands[3], p));
-  DONE;
-})
-
-(define_expand "aarch64_sqdmlsl2<mode>"
-  [(match_operand:<VWIDE> 0 "register_operand")
-   (match_operand:<VWIDE> 1 "register_operand")
-   (match_operand:VQ_HSI 2 "register_operand")
-   (match_operand:VQ_HSI 3 "register_operand")]
-  "TARGET_SIMD"
-{
-  rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true);
-  emit_insn (gen_aarch64_sqdmlsl2<mode>_internal (operands[0], operands[1],
-						  operands[2], operands[3], p));
+  emit_insn (gen_aarch64_sqdml<SBINQOPS:as>l2<mode>_internal (operands[0],
+						operands[1], operands[2],
+						operands[3], p));
   DONE;
 })
 
@@ -5436,63 +5426,37 @@
   [(set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")]
 )
 
-(define_expand "aarch64_sqdmlal2_lane<mode>"
-  [(match_operand:<VWIDE> 0 "register_operand")
-   (match_operand:<VWIDE> 1 "register_operand")
-   (match_operand:VQ_HSI 2 "register_operand")
-   (match_operand:<VCOND> 3 "register_operand")
-   (match_operand:SI 4 "immediate_operand")]
-  "TARGET_SIMD"
-{
-  rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true);
-  emit_insn (gen_aarch64_sqdmlal2_lane<mode>_internal (operands[0], operands[1],
-						       operands[2], operands[3],
-						       operands[4], p));
-  DONE;
-})
-
-(define_expand "aarch64_sqdmlal2_laneq<mode>"
-  [(match_operand:<VWIDE> 0 "register_operand")
-   (match_operand:<VWIDE> 1 "register_operand")
-   (match_operand:VQ_HSI 2 "register_operand")
-   (match_operand:<VCONQ> 3 "register_operand")
-   (match_operand:SI 4 "immediate_operand")]
-  "TARGET_SIMD"
-{
-  rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true);
-  emit_insn (gen_aarch64_sqdmlal2_laneq<mode>_internal (operands[0], operands[1],
-						       operands[2], operands[3],
-						       operands[4], p));
-  DONE;
-})
-
-(define_expand "aarch64_sqdmlsl2_lane<mode>"
+(define_expand "aarch64_sqdml<SBINQOPS:as>l2_lane<mode>"
   [(match_operand:<VWIDE> 0 "register_operand")
-   (match_operand:<VWIDE> 1 "register_operand")
+   (SBINQOPS:<VWIDE>
+     (match_operand:<VWIDE> 1 "register_operand")
+     (match_dup 1))
    (match_operand:VQ_HSI 2 "register_operand")
    (match_operand:<VCOND> 3 "register_operand")
    (match_operand:SI 4 "immediate_operand")]
   "TARGET_SIMD"
 {
   rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true);
-  emit_insn (gen_aarch64_sqdmlsl2_lane<mode>_internal (operands[0], operands[1],
-						       operands[2], operands[3],
-						       operands[4], p));
+  emit_insn (gen_aarch64_sqdml<SBINQOPS:as>l2_lane<mode>_internal (operands[0],
+						operands[1], operands[2],
+						operands[3], operands[4], p));
   DONE;
 })
 
-(define_expand "aarch64_sqdmlsl2_laneq<mode>"
+(define_expand "aarch64_sqdml<SBINQOPS:as>l2_laneq<mode>"
   [(match_operand:<VWIDE> 0 "register_operand")
-   (match_operand:<VWIDE> 1 "register_operand")
+   (SBINQOPS:<VWIDE>
+     (match_operand:<VWIDE> 1 "register_operand")
+     (match_dup 1))
    (match_operand:VQ_HSI 2 "register_operand")
    (match_operand:<VCONQ> 3 "register_operand")
    (match_operand:SI 4 "immediate_operand")]
   "TARGET_SIMD"
 {
   rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true);
-  emit_insn (gen_aarch64_sqdmlsl2_laneq<mode>_internal (operands[0], operands[1],
-						       operands[2], operands[3],
-						       operands[4], p));
+  emit_insn (gen_aarch64_sqdml<SBINQOPS:as>l2_laneq<mode>_internal (operands[0],
+						operands[1], operands[2],
+						operands[3], operands[4], p));
   DONE;
 })
 
@@ -5515,31 +5479,19 @@
   [(set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")]
 )
 
-(define_expand "aarch64_sqdmlal2_n<mode>"
-  [(match_operand:<VWIDE> 0 "register_operand")
-   (match_operand:<VWIDE> 1 "register_operand")
-   (match_operand:VQ_HSI 2 "register_operand")
-   (match_operand:<VEL> 3 "register_operand")]
-  "TARGET_SIMD"
-{
-  rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true);
-  emit_insn (gen_aarch64_sqdmlal2_n<mode>_internal (operands[0], operands[1],
-						    operands[2], operands[3],
-						    p));
-  DONE;
-})
-
-(define_expand "aarch64_sqdmlsl2_n<mode>"
+(define_expand "aarch64_sqdml<SBINQOPS:as>l2_n<mode>"
   [(match_operand:<VWIDE> 0 "register_operand")
-   (match_operand:<VWIDE> 1 "register_operand")
+   (SBINQOPS:<VWIDE>
+     (match_operand:<VWIDE> 1 "register_operand")
+     (match_dup 1))
    (match_operand:VQ_HSI 2 "register_operand")
    (match_operand:<VEL> 3 "register_operand")]
   "TARGET_SIMD"
 {
   rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true);
-  emit_insn (gen_aarch64_sqdmlsl2_n<mode>_internal (operands[0], operands[1],
-						    operands[2], operands[3],
-						    p));
+  emit_insn (gen_aarch64_sqdml<SBINQOPS:as>l2_n<mode>_internal (operands[0],
+						operands[1], operands[2],
+						operands[3], p));
   DONE;
 })