microblaze.c: Add microblaze_asm_output_mi_thunk and define TARGET_ASM_OUTPUT_MI_THUNK and...

	* config/microblaze/microblaze.c: Add microblaze_asm_output_mi_thunk
	and define TARGET_ASM_OUTPUT_MI_THUNK and
	TARGET_ASM_CAN_OUTPUT_MI_THUNK.

From-SVN: r201185

5 files changed, 66 insertions, 0 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 620ac6d..ad01f9d 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2013-07-23  David Holsgrove <david.holsgrove@xilinx.com>
+
+	* config/microblaze/microblaze.c: Add microblaze_asm_output_mi_thunk
+	and define TARGET_ASM_OUTPUT_MI_THUNK and
+	TARGET_ASM_CAN_OUTPUT_MI_THUNK.
+
 2013-07-23  Eric Botcazou  <ebotcazou@adacore.com>
 
 	* doc/invoke.texi (SPARC Options): Document new leon3 processor value.
diff --git a/gcc/config/microblaze/constraints.md b/gcc/config/microblaze/constraints.md
index c6fbc98..c9c1649 100644
--- a/gcc/config/microblaze/constraints.md
+++ b/gcc/config/microblaze/constraints.md
@@ -70,3 +70,8 @@
   "Double word operand."
   (and (match_code "mem")
        (match_test "double_memory_operand (op, GET_MODE (op))")))
+
+(define_memory_constraint "Q"
+  "Memory operand which is a single register."
+  (and (match_code "mem")
+       (match_test "GET_CODE ( XEXP (op, 0)) == REG")))
diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
index 46d07c7..649a6b7 100644
--- a/gcc/config/microblaze/microblaze.c
+++ b/gcc/config/microblaze/microblaze.c
@@ -2118,6 +2118,7 @@ microblaze_initial_elimination_offset (int from, int to)
    't'  print 't' for EQ, 'f' for NE
    'm'  Print 1<<operand.
    'i'  Print 'i' if MEM operand has immediate value
+   'y'  Print 'y' if MEM operand is single register
    'o'	Print operand address+4
    '?'	Print 'd' if we use a branch with delay slot instead of normal branch.
    'h'  Print high word of const_double (int or float) value as hex
@@ -2288,6 +2289,15 @@ print_operand (FILE * file, rtx op, int letter)
 	rtx op4 = adjust_address (op, GET_MODE (op), 4);
 	output_address (XEXP (op4, 0));
       }
+    else if (letter == 'y')
+      {
+        rtx mem_reg = XEXP (op, 0);
+        if (GET_CODE (mem_reg) == REG)
+        {
+            register int regnum = REGNO (mem_reg);
+            fprintf (file, "%s", reg_names[regnum]);
+        }
+      }
     else
       output_address (XEXP (op, 0));
 
diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
index 3618cad..40d2739 100644
--- a/gcc/config/microblaze/microblaze.md
+++ b/gcc/config/microblaze/microblaze.md
@@ -2221,3 +2221,5 @@
   [(set_attr "type"     "arith")
   (set_attr "mode"      "SI")
   (set_attr "length"    "4")])
+
+(include "sync.md")
diff --git a/gcc/config/microblaze/sync.md b/gcc/config/microblaze/sync.md
new file mode 100644
index 0000000..d880422
--- /dev/null
+++ b/gcc/config/microblaze/sync.md
@@ -0,0 +1,43 @@
+;; Machine description for Xilinx MicroBlaze synchronization instructions.
+;; Copyright (C) 2011-2013 Free Software Foundation, Inc.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published
+;; by the Free Software Foundation; either version 3, or (at your
+;; option) any later version.
+;;
+;; GCC is distributed in the hope that it will be useful, but WITHOUT
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+;; License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3.  If not see
+;; <http://www.gnu.org/licenses/>.
+
+(define_insn "atomic_compare_and_swapsi"
+  [(match_operand:SI 0 "register_operand" "=&d")	;; bool output
+   (match_operand:SI 1 "register_operand" "=&d")	;; val output
+   (match_operand:SI 2 "nonimmediate_operand" "+Q")	;; memory
+   (match_operand:SI 3 "register_operand" "d")		;; expected value
+   (match_operand:SI 4 "register_operand" "d")		;; desired value
+   (match_operand:SI 5 "const_int_operand" "")		;; is_weak
+   (match_operand:SI 6 "const_int_operand" "")		;; mod_s
+   (match_operand:SI 7 "const_int_operand" "")		;; mod_f
+   (clobber (match_scratch:SI 8 "=&d"))]
+  ""
+  {
+    output_asm_insn ("addc \tr0,r0,r0", operands);
+    output_asm_insn ("lwx  \t%1,%y2,r0", operands);
+    output_asm_insn ("addic\t%8,r0,0", operands);
+    output_asm_insn ("bnei \t%8,.-8", operands);
+    output_asm_insn ("cmp  \t%0,%1,%3", operands);
+    output_asm_insn ("bnei \t%0,.+16", operands);
+    output_asm_insn ("swx  \t%4,%y2,r0", operands);
+    output_asm_insn ("addic\t%8,r0,0", operands);
+    output_asm_insn ("bnei \t%8,.-28", operands);
+    return "";
+  }
+)