diff options
| author | Juzhe-Zhong <juzhe.zhong@rivai.ai> | 2023-08-23 10:42:01 +0800 |
|---|---|---|
| committer | Pan Li <pan2.li@intel.com> | 2023-08-23 10:48:45 +0800 |
| commit | 3beef5e6b5b12b5c90040c8485f1836e2dd6cf83 (patch) | |
| tree | 617c4f0cf0eefb68f0ed7d8362b258eb62d13878 | |
| parent | 29487eb237b893c673e9ecc6409b175e22792f13 (diff) | |
| download | gcc-3beef5e6b5b12b5c90040c8485f1836e2dd6cf83.zip gcc-3beef5e6b5b12b5c90040c8485f1836e2dd6cf83.tar.gz gcc-3beef5e6b5b12b5c90040c8485f1836e2dd6cf83.tar.bz2 | |
RISC-V: Fix potential ICE of global vsetvl elimination
Committed for following VSETVL refactor patch to make V2 patch easier to review.
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc
(pass_vsetvl::global_eliminate_vsetvl_insn): Fix potential ICE.
| -rw-r--r-- | gcc/config/riscv/riscv-vsetvl.cc | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc index ec1aaa4..f7558ca 100644 --- a/gcc/config/riscv/riscv-vsetvl.cc +++ b/gcc/config/riscv/riscv-vsetvl.cc @@ -4383,7 +4383,7 @@ pass_vsetvl::global_eliminate_vsetvl_insn (const bb_info *bb) const unsigned int bb_index; sbitmap_iterator sbi; - rtx avl = get_avl (dem.get_insn ()->rtl ()); + rtx avl = dem.get_avl (); hash_set<set_info *> sets = get_all_sets (dem.get_avl_source (), true, false, false); /* Condition 2: All VL/VTYPE available in are all compatible. */ @@ -4407,7 +4407,10 @@ pass_vsetvl::global_eliminate_vsetvl_insn (const bb_info *bb) const { sbitmap avout = m_vector_manager->vector_avout[e->src->index]; if (e->src == ENTRY_BLOCK_PTR_FOR_FN (cfun) - || e->src == EXIT_BLOCK_PTR_FOR_FN (cfun) || bitmap_empty_p (avout)) + || e->src == EXIT_BLOCK_PTR_FOR_FN (cfun) + || (unsigned int) e->src->index + >= m_vector_manager->vector_block_infos.length () + || bitmap_empty_p (avout)) return false; EXECUTE_IF_SET_IN_BITMAP (avout, 0, bb_index, sbi) |