diff options
| author | Kito Cheng <kito.cheng@sifive.com> | 2024-02-16 17:27:24 +0800 |
|---|---|---|
| committer | Kito Cheng <kito.cheng@sifive.com> | 2024-02-16 18:09:43 +0800 |
| commit | 325d5dd53270fe8fd62b36c92c8f8b87c2938bf1 (patch) | |
| tree | b8a7667f768daa2449c1d13d216a6e9a878503a8 | |
| parent | de658585d6dcc89f1cba71ef5f8f5b55719a7054 (diff) | |
| download | gcc-325d5dd53270fe8fd62b36c92c8f8b87c2938bf1.zip gcc-325d5dd53270fe8fd62b36c92c8f8b87c2938bf1.tar.gz gcc-325d5dd53270fe8fd62b36c92c8f8b87c2938bf1.tar.bz2 | |
RISC-V: Fix *sge<u>_<X:mode><GPR:mode> pattern
*sge<u>_<X:mode><GPR:mode> pattern has referenced operand[2] which is
invalid...it should just use `slti<u>` rather than `slti%i2<u>`.
gcc/ChangeLog:
PR target/106543
* config/riscv/riscv.md (*sge<u>_<X:mode><GPR:mode>): Fix asm
pattern.
| -rw-r--r-- | gcc/config/riscv/riscv.md | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 39b2979..3f7a023 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -3107,7 +3107,7 @@ (any_ge:GPR (match_operand:X 1 "register_operand" " r") (const_int 1)))] "" - "slt%i2<u>\t%0,zero,%1" + "slti<u>\t%0,zero,%1" [(set_attr "type" "slt") (set_attr "mode" "<X:MODE>")]) |