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| author | Claudiu Zissulescu <claziss@synopsys.com> | 2018-07-16 12:12:47 +0200 |
|---|---|---|
| committer | Claudiu Zissulescu <claziss@gcc.gnu.org> | 2018-07-16 12:12:47 +0200 |
| commit | 325a4c6e1100ef4cf88dc007c64d20fe9b9a6c2c (patch) | |
| tree | 38f35ffb12fdc31c4902df67c445f7eeceab1c5b | |
| parent | 43bb0fc221b05f67c01879c741c321ad0a67fddf (diff) | |
| download | gcc-325a4c6e1100ef4cf88dc007c64d20fe9b9a6c2c.zip gcc-325a4c6e1100ef4cf88dc007c64d20fe9b9a6c2c.tar.gz gcc-325a4c6e1100ef4cf88dc007c64d20fe9b9a6c2c.tar.bz2 | |
[ARC] Update ARCHS scheduling rules.
2017-07-16 Claudiu Zissulescu <claziss@synopsys.com>
* config/arc/arcHS.md: Update ARCHS scheduling rules.
From-SVN: r262689
| -rw-r--r-- | gcc/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/config/arc/arcHS.md | 21 |
2 files changed, 19 insertions, 6 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index c8a00cc..a0f3c52 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,9 @@ 2017-07-16 Claudiu Zissulescu <claziss@synopsys.com> + * config/arc/arcHS.md: Update ARCHS scheduling rules. + +2017-07-16 Claudiu Zissulescu <claziss@synopsys.com> + * config/arc/arc-arch.h (arc_tune_attr): Add new tune parameters for ARCHS4x. * config/arc/arc-cpus.def (hs4x): New cpu. diff --git a/gcc/config/arc/arcHS.md b/gcc/config/arc/arcHS.md index d49b90c..5c1ab54 100644 --- a/gcc/config/arc/arcHS.md +++ b/gcc/config/arc/arcHS.md @@ -35,12 +35,14 @@ (eq_attr "type" "store")) "hs_issue+hs_ld_st") -(define_insn_reservation "hs_alu0" 2 +;; Advanced ALU +(define_insn_reservation "hs_alu0" 4 (and (match_test "TARGET_HS") (eq_attr "tune" "none") (eq_attr "type" "cc_arith, two_cycle_core, shift, lr, sr")) - "hs_issue+x1,x2") + "hs_issue+x1,x2, nothing*2") +;; Basic ALU (define_insn_reservation "hs_alu1" 4 (and (match_test "TARGET_HS") (eq_attr "tune" "none") @@ -54,19 +56,26 @@ (eq_attr "type" "div_rem")) "hs_issue+divrem_hs, (divrem_hs)*12") -(define_insn_reservation "hs_mul" 3 +(define_insn_reservation "hs_mul" 4 (and (match_test "TARGET_HS") (eq_attr "tune" "none") (eq_attr "type" "mul16_em, multi, umulti")) "hs_issue+mul_hs, nothing*3") -;; BYPASS EALU -> +;; BYPASS Advanced ALU -> (define_bypass 1 "hs_alu0" "hs_divrem") (define_bypass 1 "hs_alu0" "hs_mul") +(define_bypass 2 "hs_alu0" "hs_alu0") +(define_bypass 1 "hs_alu0" "hs_alu1") +(define_bypass 1 "hs_alu0" "hs_data_load") +(define_bypass 1 "hs_alu0" "hs_data_store" "store_data_bypass_p") +(define_bypass 2 "hs_alu0" "hs_data_store") -;; BYPASS BALU -> +;; BYPASS Basic ALU -> (define_bypass 1 "hs_alu1" "hs_alu1") (define_bypass 1 "hs_alu1" "hs_data_store" "store_data_bypass_p") +(define_bypass 3 "hs_alu1" "hs_mul") +(define_bypass 3 "hs_alu1" "hs_divrem") ;; BYPASS LD -> (define_bypass 1 "hs_data_load" "hs_alu1") @@ -76,7 +85,7 @@ (define_bypass 1 "hs_data_load" "hs_data_store" "store_data_bypass_p") ;; BYPASS MPY -> -;;(define_bypass 3 "hs_mul" "hs_mul") +(define_bypass 3 "hs_mul" "hs_mul") (define_bypass 1 "hs_mul" "hs_alu1") (define_bypass 3 "hs_mul" "hs_divrem") (define_bypass 1 "hs_mul" "hs_data_store" "store_data_bypass_p") |