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| author | Richard Sandiford <richard.sandiford@linaro.org> | 2017-12-21 07:01:17 +0000 |
|---|---|---|
| committer | Richard Sandiford <rsandifo@gcc.gnu.org> | 2017-12-21 07:01:17 +0000 |
| commit | 31ae0e43aac40d1c45d00be9cda260c30d87d154 (patch) | |
| tree | 9017583d11ad940833a5b13cb2b820f92e05c7d9 | |
| parent | 5e48d89420f8b16c1eddb9b568c4fee74eefbd45 (diff) | |
| download | gcc-31ae0e43aac40d1c45d00be9cda260c30d87d154.zip gcc-31ae0e43aac40d1c45d00be9cda260c30d87d154.tar.gz gcc-31ae0e43aac40d1c45d00be9cda260c30d87d154.tar.bz2 | |
poly_int: emit_inc
This patch changes the LRA emit_inc routine so that it takes
a poly_int64 rather than an int.
2017-12-21 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* lra-constraints.c (emit_inc): Change inc_amount from an int
to a poly_int64.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r255923
| -rw-r--r-- | gcc/ChangeLog | 7 | ||||
| -rw-r--r-- | gcc/lra-constraints.c | 4 |
2 files changed, 9 insertions, 2 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 30abd3d..f633487 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -2,6 +2,13 @@ Alan Hayward <alan.hayward@arm.com> David Sherwood <david.sherwood@arm.com> + * lra-constraints.c (emit_inc): Change inc_amount from an int + to a poly_int64. + +2017-12-21 Richard Sandiford <richard.sandiford@linaro.org> + Alan Hayward <alan.hayward@arm.com> + David Sherwood <david.sherwood@arm.com> + * cfgexpand.c (stack_var::size): Change from a HOST_WIDE_INT to a poly_uint64. (add_stack_var, stack_var_cmp, partition_stack_vars) diff --git a/gcc/lra-constraints.c b/gcc/lra-constraints.c index de45d2c..73ffba2 100644 --- a/gcc/lra-constraints.c +++ b/gcc/lra-constraints.c @@ -3534,7 +3534,7 @@ process_address (int nop, bool check_only_p, Return pseudo containing the result. */ static rtx -emit_inc (enum reg_class new_rclass, rtx in, rtx value, int inc_amount) +emit_inc (enum reg_class new_rclass, rtx in, rtx value, poly_int64 inc_amount) { /* REG or MEM to be copied and incremented. */ rtx incloc = XEXP (value, 0); @@ -3562,7 +3562,7 @@ emit_inc (enum reg_class new_rclass, rtx in, rtx value, int inc_amount) if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC) inc_amount = -inc_amount; - inc = GEN_INT (inc_amount); + inc = gen_int_mode (inc_amount, GET_MODE (value)); } if (! post && REG_P (incloc)) |