diff options
| author | Tamar Christina <tamar.christina@arm.com> | 2024-01-24 15:56:50 +0000 |
|---|---|---|
| committer | Tamar Christina <tamar.christina@arm.com> | 2024-01-24 15:56:50 +0000 |
| commit | 306713c953d509720dc394c43c0890548bb0ae07 (patch) | |
| tree | 6f4f344ce07e777847540fc7bef95004f6537941 | |
| parent | bc4a20bc57ce71da0a96bcc6ec5683640b9004d6 (diff) | |
| download | gcc-306713c953d509720dc394c43c0890548bb0ae07.zip gcc-306713c953d509720dc394c43c0890548bb0ae07.tar.gz gcc-306713c953d509720dc394c43c0890548bb0ae07.tar.bz2 | |
AArch64: Do not allow SIMD clones with simdlen 1 [PR113552]
The AArch64 vector PCS does not allow simd calls with simdlen 1,
however due to a bug we currently do allow it for num == 0.
This causes us to emit a symbol that doesn't exist and we fail to link.
gcc/ChangeLog:
PR tree-optimization/113552
* config/aarch64/aarch64.cc
(aarch64_simd_clone_compute_vecsize_and_simdlen): Block simdlen 1.
gcc/testsuite/ChangeLog:
PR tree-optimization/113552
* gcc.target/aarch64/pr113552.c: New test.
* gcc.target/aarch64/simd_pcs_attribute-3.c: Remove bogus check.
| -rw-r--r-- | gcc/config/aarch64/aarch64.cc | 3 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/pr113552.c | 17 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/simd_pcs_attribute-3.c | 4 |
3 files changed, 21 insertions, 3 deletions
diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc index e6bd3fd..c54b606 100644 --- a/gcc/config/aarch64/aarch64.cc +++ b/gcc/config/aarch64/aarch64.cc @@ -28620,7 +28620,8 @@ aarch64_simd_clone_compute_vecsize_and_simdlen (struct cgraph_node *node, if (known_eq (clonei->simdlen, 0U)) { simdlen = exact_div (poly_uint64 (64), nds_elt_bits); - simdlens.safe_push (simdlen); + if (maybe_ne (simdlen, 1U)) + simdlens.safe_push (simdlen); simdlens.safe_push (simdlen * 2); } else diff --git a/gcc/testsuite/gcc.target/aarch64/pr113552.c b/gcc/testsuite/gcc.target/aarch64/pr113552.c new file mode 100644 index 0000000..9c96b06 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/pr113552.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-Ofast -march=armv8-a" } */ + +__attribute__ ((__simd__ ("notinbranch"), const)) +double cos (double); + +void foo (float *a, double *b) +{ + for (int i = 0; i < 12; i+=3) + { + b[i] = cos (5.0 * a[i]); + b[i+1] = cos (5.0 * a[i+1]); + b[i+2] = cos (5.0 * a[i+2]); + } +} + +/* { dg-final { scan-assembler-times {bl\t_ZGVnN2v_cos} 6 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/simd_pcs_attribute-3.c b/gcc/testsuite/gcc.target/aarch64/simd_pcs_attribute-3.c index 95f6a68..c6dac6b 100644 --- a/gcc/testsuite/gcc.target/aarch64/simd_pcs_attribute-3.c +++ b/gcc/testsuite/gcc.target/aarch64/simd_pcs_attribute-3.c @@ -18,7 +18,7 @@ double foo(double x) } /* { dg-final { scan-assembler-not {\.variant_pcs\tfoo} } } */ -/* { dg-final { scan-assembler-times {\.variant_pcs\t_ZGVnM1v_foo} 1 } } */ +/* { dg-final { scan-assembler-not {\.variant_pcs\t_ZGVnM1v_foo} } } */ /* { dg-final { scan-assembler-times {\.variant_pcs\t_ZGVnM2v_foo} 1 } } */ -/* { dg-final { scan-assembler-times {\.variant_pcs\t_ZGVnN1v_foo} 1 } } */ +/* { dg-final { scan-assembler-not {\.variant_pcs\t_ZGVnN1v_foo} } } */ /* { dg-final { scan-assembler-times {\.variant_pcs\t_ZGVnN2v_foo} 1 } } */ |