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| author | Philipp Tomsich <philipp.tomsich@vrull.eu> | 2022-11-10 00:43:05 +0100 |
|---|---|---|
| committer | Philipp Tomsich <philipp.tomsich@vrull.eu> | 2022-11-10 14:57:02 +0100 |
| commit | 2f6cb9c51a933de19cd88f4c9180ac9cf5093522 (patch) | |
| tree | fa7d78125227177882b17534e6e31dfcd3f2c555 | |
| parent | 203b127fccc9abe5373c9e3cc03a476c35b1f594 (diff) | |
| download | gcc-2f6cb9c51a933de19cd88f4c9180ac9cf5093522.zip gcc-2f6cb9c51a933de19cd88f4c9180ac9cf5093522.tar.gz gcc-2f6cb9c51a933de19cd88f4c9180ac9cf5093522.tar.bz2 | |
RISC-V: Fix selection of pipeline model for sifive-7-series
A few of the gcc.target/riscv/mcpu-*.c tests have been failing for a
while now, due to the pipeline model for sifive-7-series not being
selected despite -mtune=sifive-7-series. The root cause is that the
respective RISCV_TUNE entry points to generic instead. Fix this.
Fixes 97d1ed67fc6 ("RISC-V: Support --target-help for -mcpu/-mtune")
gcc/ChangeLog:
* config/riscv/riscv-cores.def (RISCV_TUNE): Update
sifive-7-series to point to the sifive_7 pipeline description.
| -rw-r--r-- | gcc/config/riscv/riscv-cores.def | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def index b84ad99..31ad346 100644 --- a/gcc/config/riscv/riscv-cores.def +++ b/gcc/config/riscv/riscv-cores.def @@ -36,7 +36,7 @@ RISCV_TUNE("rocket", generic, rocket_tune_info) RISCV_TUNE("sifive-3-series", generic, rocket_tune_info) RISCV_TUNE("sifive-5-series", generic, rocket_tune_info) -RISCV_TUNE("sifive-7-series", generic, sifive_7_tune_info) +RISCV_TUNE("sifive-7-series", sifive_7, sifive_7_tune_info) RISCV_TUNE("thead-c906", generic, thead_c906_tune_info) RISCV_TUNE("size", generic, optimize_size_tune_info) |